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0c9654072a
- Move code that can be shared with XLP (irq.c, smp.c, time.c and xlr_console.c) to arch/mips/netlogic/common - Add asm/netlogic/haldefs.h and asm/netlogic/common.h for common and io functions shared with XLP - remove type 'nlm_reg_t *' and use uint64_t for mmio offsets - Move XLR specific code in smp.c to xlr/wakeup.c - Move XLR specific PCI code from irq.c to mips/pci/pci-xlr.c - Provide API for pic functions called from common/irq.c Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2964/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
100 lines
2.8 KiB
ArmAsm
100 lines
2.8 KiB
ArmAsm
/*
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
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* reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the NetLogic
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/init.h>
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#include <asm/asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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/*
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* Early code for secondary CPUs. This will get them out of the bootloader
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* code and into linux. Needed because the bootloader area will be taken
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* and initialized by linux.
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*/
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__CPUINIT
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NESTED(prom_pre_boot_secondary_cpus, 16, sp)
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.set mips64
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mfc0 t0, $15, 1 # read ebase
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andi t0, 0x1f # t0 has the processor_id()
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sll t0, 2 # offset in cpu array
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PTR_LA t1, nlm_cpu_ready # mark CPU ready
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PTR_ADDU t1, t0
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li t2, 1
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sw t2, 0(t1)
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PTR_LA t1, nlm_cpu_unblock
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PTR_ADDU t1, t0
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1: lw t2, 0(t1) # wait till unblocked
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beqz t2, 1b
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nop
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PTR_LA t1, nlm_next_sp
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PTR_L sp, 0(t1)
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PTR_LA t1, nlm_next_gp
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PTR_L gp, 0(t1)
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PTR_LA t0, nlm_early_init_secondary
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jalr t0
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nop
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PTR_LA t0, smp_bootstrap
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jr t0
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nop
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END(prom_pre_boot_secondary_cpus)
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/*
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* NMI code, used for CPU wakeup, copied to reset entry
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*/
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EXPORT(nlm_reset_entry)
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.set push
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.set noat
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.set mips64
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.set noreorder
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/* Clear the NMI and BEV bits */
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MFC0 k0, CP0_STATUS
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li k1, 0xffb7ffff
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and k0, k0, k1
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MTC0 k0, CP0_STATUS
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PTR_LA k1, secondary_entry_point
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PTR_L k0, 0(k1)
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jr k0
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nop
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.set pop
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EXPORT(nlm_reset_entry_end)
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__FINIT
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