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878b9e944c
umc query_ras_error_count will be invoked to query umc correctable and uncorrectable error. It will reset the umc ras error counter after the query. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
189 lines
6.5 KiB
C
189 lines
6.5 KiB
C
/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "umc_v6_7.h"
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#include "amdgpu_ras.h"
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#include "amdgpu.h"
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#include "umc/umc_6_7_0_offset.h"
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#include "umc/umc_6_7_0_sh_mask.h"
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static inline uint32_t get_umc_v6_7_reg_offset(struct amdgpu_device *adev,
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uint32_t umc_inst,
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uint32_t ch_inst)
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{
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return adev->umc.channel_offs * ch_inst + UMC_V6_7_INST_DIST * umc_inst;
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}
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static void umc_v6_7_query_correctable_error_count(struct amdgpu_device *adev,
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uint32_t umc_reg_offset,
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unsigned long *error_count)
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{
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uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;
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uint32_t ecc_err_cnt, ecc_err_cnt_addr;
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uint64_t mc_umc_status;
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uint32_t mc_umc_status_addr;
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/* UMC 6_1_1 registers */
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ecc_err_cnt_sel_addr =
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SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_EccErrCntSel);
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ecc_err_cnt_addr =
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SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_EccErrCnt);
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mc_umc_status_addr =
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SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
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/* select the lower chip and check the error count */
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ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4);
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ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
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EccErrCntCsSel, 0);
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WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel);
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ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4);
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*error_count +=
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(REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) -
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UMC_V6_7_CE_CNT_INIT);
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/* select the higher chip and check the err counter */
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ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
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EccErrCntCsSel, 1);
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WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel);
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ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4);
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*error_count +=
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(REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) -
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UMC_V6_7_CE_CNT_INIT);
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/* check for SRAM correctable error
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MCUMC_STATUS is a 64 bit register */
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mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);
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if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
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*error_count += 1;
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}
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static void umc_v6_7_querry_uncorrectable_error_count(struct amdgpu_device *adev,
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uint32_t umc_reg_offset,
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unsigned long *error_count)
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{
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uint64_t mc_umc_status;
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uint32_t mc_umc_status_addr;
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mc_umc_status_addr =
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SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
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/* check the MCUMC_STATUS */
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mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);
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if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
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(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
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*error_count += 1;
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}
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static void umc_v6_7_reset_error_count_per_channel(struct amdgpu_device *adev,
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uint32_t umc_reg_offset)
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{
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uint32_t ecc_err_cnt_addr;
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uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;
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ecc_err_cnt_sel_addr =
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SOC15_REG_OFFSET(UMC, 0,
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regUMCCH0_0_EccErrCntSel);
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ecc_err_cnt_addr =
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SOC15_REG_OFFSET(UMC, 0,
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regUMCCH0_0_EccErrCnt);
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/* select the lower chip */
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ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr +
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umc_reg_offset) * 4);
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ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel,
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UMCCH0_0_EccErrCntSel,
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EccErrCntCsSel, 0);
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WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4,
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ecc_err_cnt_sel);
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/* clear lower chip error count */
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WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4,
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UMC_V6_7_CE_CNT_INIT);
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/* select the higher chip */
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ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr +
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umc_reg_offset) * 4);
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ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel,
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UMCCH0_0_EccErrCntSel,
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EccErrCntCsSel, 1);
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WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4,
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ecc_err_cnt_sel);
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/* clear higher chip error count */
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WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4,
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UMC_V6_7_CE_CNT_INIT);
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}
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static void umc_v6_7_reset_error_count(struct amdgpu_device *adev)
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{
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uint32_t umc_inst = 0;
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uint32_t ch_inst = 0;
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uint32_t umc_reg_offset = 0;
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LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
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umc_reg_offset = get_umc_v6_7_reg_offset(adev,
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umc_inst,
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ch_inst);
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umc_v6_7_reset_error_count_per_channel(adev,
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umc_reg_offset);
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}
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}
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static void umc_v6_7_query_ras_error_count(struct amdgpu_device *adev,
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void *ras_error_status)
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{
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struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
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uint32_t umc_inst = 0;
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uint32_t ch_inst = 0;
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uint32_t umc_reg_offset = 0;
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/*TODO: driver needs to toggle DF Cstate to ensure
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* safe access of UMC registers. Will add the protection */
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LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
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umc_reg_offset = get_umc_v6_7_reg_offset(adev,
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umc_inst,
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ch_inst);
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umc_v6_7_query_correctable_error_count(adev,
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umc_reg_offset,
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&(err_data->ce_count));
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umc_v6_7_querry_uncorrectable_error_count(adev,
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umc_reg_offset,
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&(err_data->ue_count));
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}
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umc_v6_7_reset_error_count(adev);
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}
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const struct amdgpu_umc_funcs umc_v6_7_funcs = {
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.ras_late_init = amdgpu_umc_ras_late_init,
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.query_ras_error_count = umc_v6_7_query_ras_error_count,
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};
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