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85848dd7ab
ARMv7 processors like Cortex-A9 broadcast the cache maintenance operations in hardware. This patch allows the flush_dcache_page/update_mmu_cache pair to work in lazy flushing mode similar to the UP case. Note that cache flushing on SMP systems now takes place via the set_pte_at() call (__sync_icache_dcache) and there is no race with other CPUs executing code from the new PTE before the cache flushing took place. Tested-by: Rabin Vincent <rabin.vincent@stericsson.com> Cc: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
25 lines
563 B
C
25 lines
563 B
C
/*
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* ARM specific SMP header, this contains our implementation
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* details.
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*/
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#ifndef __ASMARM_SMP_PLAT_H
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#define __ASMARM_SMP_PLAT_H
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#include <asm/cputype.h>
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/* all SMP configurations have the extended CPUID registers */
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static inline int tlb_ops_need_broadcast(void)
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{
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return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
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}
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#if !defined(CONFIG_SMP) || __LINUX_ARM_ARCH__ >= 7
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#define cache_ops_need_broadcast() 0
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#else
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static inline int cache_ops_need_broadcast(void)
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{
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return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
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}
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#endif
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#endif
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