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81b437f57e
[Why] When changing pixel formats for HDR (e.g. ARGB -> FP16) there are configurations that change from 2 pipes to 1 pipe. In these cases, it seems that disconnecting MPCC and doing a surface update at the same time(after unlocking) causes some registers to be updated slightly faster than others after unlocking (e.g. if the pixel format is updated to FP16 before the new surface address is programmed, we get corruption on the screen because the pixel formats aren't matching). We separate disconnecting MPCC from the rest of the pipe programming sequence to prevent this. [How] Move MPCC disconnect into separate operation than the rest of the pipe programming. Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
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| .. | ||
| hw | ||
| bw_fixed.h | ||
| clock_source.h | ||
| compressor.h | ||
| core_status.h | ||
| core_types.h | ||
| custom_float.h | ||
| dc_link_ddc.h | ||
| dc_link_dp.h | ||
| dce_calcs.h | ||
| dcn_calc_math.h | ||
| dcn_calcs.h | ||
| hw_sequencer.h | ||
| hw_sequencer_private.h | ||
| link_hwss.h | ||
| reg_helper.h | ||
| resource.h | ||
| vm_helper.h | ||