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802b83627f
Use a new config option to enable R4600 V1 index I-cacheop workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
23 lines
628 B
C
23 lines
628 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
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*/
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#ifndef __ASM_MIPS_MACH_IP30_WAR_H
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#define __ASM_MIPS_MACH_IP30_WAR_H
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define MIPS4K_ICACHE_REFILL_WAR 0
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#define MIPS_CACHE_SYNC_WAR 0
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#define TX49XX_ICACHE_INDEX_INV_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#ifdef CONFIG_CPU_R10000
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#define R10000_LLSC_WAR 1
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#else
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#define R10000_LLSC_WAR 0
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#endif
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#define MIPS34K_MISSED_ITLB_WAR 0
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#endif /* __ASM_MIPS_MACH_IP30_WAR_H */
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