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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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7dbde76316
Intel TDX protects guest memory from VMM access. Any memory that is required for communication with the VMM must be explicitly shared. It is a two-step process: the guest sets the shared bit in the page table entry and notifies VMM about the change. The notification happens using MapGPA hypercall. Conversion back to private memory requires clearing the shared bit, notifying VMM with MapGPA hypercall following with accepting the memory with AcceptPage hypercall. Provide a TDX version of x86_platform.guest.* callbacks. It makes __set_memory_enc_pgtable() work right in TDX guest. Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/20220405232939.73860-27-kirill.shutemov@linux.intel.com
136 lines
3 KiB
C
136 lines
3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Confidential Computing Platform Capability checks
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*
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* Copyright (C) 2021 Advanced Micro Devices, Inc.
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*
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* Author: Tom Lendacky <thomas.lendacky@amd.com>
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*/
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#include <linux/export.h>
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#include <linux/cc_platform.h>
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#include <asm/coco.h>
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#include <asm/processor.h>
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static enum cc_vendor vendor __ro_after_init;
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static u64 cc_mask __ro_after_init;
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static bool intel_cc_platform_has(enum cc_attr attr)
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{
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switch (attr) {
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case CC_ATTR_GUEST_UNROLL_STRING_IO:
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case CC_ATTR_HOTPLUG_DISABLED:
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case CC_ATTR_GUEST_MEM_ENCRYPT:
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return true;
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default:
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return false;
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}
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}
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/*
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* SME and SEV are very similar but they are not the same, so there are
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* times that the kernel will need to distinguish between SME and SEV. The
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* cc_platform_has() function is used for this. When a distinction isn't
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* needed, the CC_ATTR_MEM_ENCRYPT attribute can be used.
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*
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* The trampoline code is a good example for this requirement. Before
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* paging is activated, SME will access all memory as decrypted, but SEV
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* will access all memory as encrypted. So, when APs are being brought
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* up under SME the trampoline area cannot be encrypted, whereas under SEV
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* the trampoline area must be encrypted.
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*/
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static bool amd_cc_platform_has(enum cc_attr attr)
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{
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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switch (attr) {
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case CC_ATTR_MEM_ENCRYPT:
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return sme_me_mask;
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case CC_ATTR_HOST_MEM_ENCRYPT:
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return sme_me_mask && !(sev_status & MSR_AMD64_SEV_ENABLED);
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case CC_ATTR_GUEST_MEM_ENCRYPT:
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return sev_status & MSR_AMD64_SEV_ENABLED;
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case CC_ATTR_GUEST_STATE_ENCRYPT:
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return sev_status & MSR_AMD64_SEV_ES_ENABLED;
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/*
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* With SEV, the rep string I/O instructions need to be unrolled
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* but SEV-ES supports them through the #VC handler.
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*/
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case CC_ATTR_GUEST_UNROLL_STRING_IO:
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return (sev_status & MSR_AMD64_SEV_ENABLED) &&
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!(sev_status & MSR_AMD64_SEV_ES_ENABLED);
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default:
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return false;
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}
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#else
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return false;
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#endif
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}
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static bool hyperv_cc_platform_has(enum cc_attr attr)
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{
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return attr == CC_ATTR_GUEST_MEM_ENCRYPT;
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}
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bool cc_platform_has(enum cc_attr attr)
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{
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switch (vendor) {
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case CC_VENDOR_AMD:
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return amd_cc_platform_has(attr);
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case CC_VENDOR_INTEL:
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return intel_cc_platform_has(attr);
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case CC_VENDOR_HYPERV:
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return hyperv_cc_platform_has(attr);
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default:
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return false;
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}
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}
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EXPORT_SYMBOL_GPL(cc_platform_has);
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u64 cc_mkenc(u64 val)
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{
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/*
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* Both AMD and Intel use a bit in the page table to indicate
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* encryption status of the page.
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*
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* - for AMD, bit *set* means the page is encrypted
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* - for Intel *clear* means encrypted.
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*/
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switch (vendor) {
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case CC_VENDOR_AMD:
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return val | cc_mask;
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case CC_VENDOR_INTEL:
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return val & ~cc_mask;
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default:
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return val;
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}
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}
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u64 cc_mkdec(u64 val)
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{
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/* See comment in cc_mkenc() */
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switch (vendor) {
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case CC_VENDOR_AMD:
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return val & ~cc_mask;
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case CC_VENDOR_INTEL:
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return val | cc_mask;
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default:
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return val;
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}
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}
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EXPORT_SYMBOL_GPL(cc_mkdec);
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__init void cc_set_vendor(enum cc_vendor v)
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{
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vendor = v;
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}
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__init void cc_set_mask(u64 mask)
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{
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cc_mask = mask;
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}
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