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7d71db537b
Add a main cache_cpu_init() init routine which initializes MTRR and/or PAT support depending on what has been detected on the system. Leave the MTRR-specific initialization in a MTRR-specific init function where the smp_changes_mask setting happens now with caches disabled. This global mask update was done with caches enabled before probably because atomic operations while running uncached might have been quite expensive. But since only systems with a broken BIOS should ever require to set any bit in smp_changes_mask, hurting those devices with a penalty of a few microseconds during boot shouldn't be a real issue. Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lore.kernel.org/r/20221102074713.21493-8-jgross@suse.com Signed-off-by: Borislav Petkov <bp@suse.de>
17 lines
479 B
C
17 lines
479 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_CACHEINFO_H
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#define _ASM_X86_CACHEINFO_H
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/* Kernel controls MTRR and/or PAT MSRs. */
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extern unsigned int memory_caching_control;
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#define CACHE_MTRR 0x01
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#define CACHE_PAT 0x02
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void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu);
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void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu);
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void cache_disable(void);
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void cache_enable(void);
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void cache_cpu_init(void);
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#endif /* _ASM_X86_CACHEINFO_H */
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