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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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4152e4206c
For QCA6390, only one pdev is created and this pdev manages both lmacs, thus both rxdmas. So host needs to initialize all rxdma related rings for one pdev. Another difference is for QCA6390, host fills rxbuf to firmware and firmware further fills the rxbuf to rxbuf ring for each rxdma. Tested-on: QCA6390 hw2.0 PCI WLAN.HST.1.0.1-01740-QCAHSTSWPLZ_V2_TO_X86-1 Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.1.0.1-01238-QCAHKSWPL_SILICONZ-2 Signed-off-by: Carl Huang <cjhuang@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/1597555891-26112-4-git-send-email-kvalo@codeaurora.org
378 lines
12 KiB
C
378 lines
12 KiB
C
// SPDX-License-Identifier: BSD-3-Clause-Clear
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/*
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* Copyright (c) 2018-2020 The Linux Foundation. All rights reserved.
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*/
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#include <linux/types.h>
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#include <linux/bitops.h>
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#include <linux/bitfield.h>
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#include "hw.h"
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#include "core.h"
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#include "ce.h"
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/* Map from pdev index to hw mac index */
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static u8 ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx)
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{
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switch (pdev_idx) {
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case 0:
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return 0;
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case 1:
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return 2;
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case 2:
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return 1;
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default:
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return ATH11K_INVALID_HW_MAC_ID;
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}
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}
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static u8 ath11k_hw_ipq6018_mac_from_pdev_id(int pdev_idx)
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{
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return pdev_idx;
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}
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static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab,
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struct target_resource_config *config)
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{
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config->num_vdevs = 4;
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config->num_peers = 16;
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config->num_tids = 32;
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config->num_offload_peers = 3;
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config->num_offload_reorder_buffs = 3;
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config->num_peer_keys = TARGET_NUM_PEER_KEYS;
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config->ast_skid_limit = TARGET_AST_SKID_LIMIT;
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config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
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config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
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config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI;
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config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI;
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config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI;
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config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI;
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config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI;
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config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS;
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config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV;
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config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV;
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config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES;
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config->num_mcast_groups = 0;
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config->num_mcast_table_elems = 0;
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config->mcast2ucast_mode = 0;
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config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE;
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config->num_wds_entries = 0;
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config->dma_burst_size = 0;
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config->rx_skip_defrag_timeout_dup_detection_check = 0;
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config->vow_config = TARGET_VOW_CONFIG;
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config->gtk_offload_max_vdev = 2;
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config->num_msdu_desc = 0x400;
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config->beacon_tx_offload_max_vdev = 2;
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config->rx_batchmode = TARGET_RX_BATCHMODE;
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config->peer_map_unmap_v2_support = 0;
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config->use_pdev_id = 1;
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config->max_frag_entries = 0xa;
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config->num_tdls_vdevs = 0x1;
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config->num_tdls_conn_table_entries = 8;
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config->beacon_tx_offload_max_vdev = 0x2;
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config->num_multicast_filter_entries = 0x20;
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config->num_wow_filters = 0x16;
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config->num_keep_alive_pattern = 0x1;
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config->num_keep_alive_pattern = 0;
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}
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static void ath11k_init_wmi_config_ipq8074(struct ath11k_base *ab,
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struct target_resource_config *config)
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{
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config->num_vdevs = ab->num_radios * TARGET_NUM_VDEVS;
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if (ab->num_radios == 2) {
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config->num_peers = TARGET_NUM_PEERS(DBS);
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config->num_tids = TARGET_NUM_TIDS(DBS);
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} else if (ab->num_radios == 3) {
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config->num_peers = TARGET_NUM_PEERS(DBS_SBS);
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config->num_tids = TARGET_NUM_TIDS(DBS_SBS);
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} else {
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/* Control should not reach here */
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config->num_peers = TARGET_NUM_PEERS(SINGLE);
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config->num_tids = TARGET_NUM_TIDS(SINGLE);
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}
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config->num_offload_peers = TARGET_NUM_OFFLD_PEERS;
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config->num_offload_reorder_buffs = TARGET_NUM_OFFLD_REORDER_BUFFS;
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config->num_peer_keys = TARGET_NUM_PEER_KEYS;
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config->ast_skid_limit = TARGET_AST_SKID_LIMIT;
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config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
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config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
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config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI;
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config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI;
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config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI;
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config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI;
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config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI;
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config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS;
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config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV;
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config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV;
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config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES;
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config->num_mcast_groups = TARGET_NUM_MCAST_GROUPS;
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config->num_mcast_table_elems = TARGET_NUM_MCAST_TABLE_ELEMS;
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config->mcast2ucast_mode = TARGET_MCAST2UCAST_MODE;
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config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE;
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config->num_wds_entries = TARGET_NUM_WDS_ENTRIES;
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config->dma_burst_size = TARGET_DMA_BURST_SIZE;
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config->rx_skip_defrag_timeout_dup_detection_check =
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TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK;
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config->vow_config = TARGET_VOW_CONFIG;
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config->gtk_offload_max_vdev = TARGET_GTK_OFFLOAD_MAX_VDEV;
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config->num_msdu_desc = TARGET_NUM_MSDU_DESC;
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config->beacon_tx_offload_max_vdev = ab->num_radios * TARGET_MAX_BCN_OFFLD;
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config->rx_batchmode = TARGET_RX_BATCHMODE;
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config->peer_map_unmap_v2_support = 1;
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config->twt_ap_pdev_count = 2;
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config->twt_ap_sta_count = 1000;
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}
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static int ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params *hw,
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int mac_id)
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{
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return mac_id;
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}
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static int ath11k_hw_mac_id_to_srng_id_ipq8074(struct ath11k_hw_params *hw,
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int mac_id)
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{
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return 0;
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}
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static int ath11k_hw_mac_id_to_pdev_id_qca6390(struct ath11k_hw_params *hw,
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int mac_id)
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{
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return 0;
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}
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static int ath11k_hw_mac_id_to_srng_id_qca6390(struct ath11k_hw_params *hw,
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int mac_id)
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{
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return mac_id;
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}
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const struct ath11k_hw_ops ipq8074_ops = {
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.get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
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.wmi_init_config = ath11k_init_wmi_config_qca6390,
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.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074,
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.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074,
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};
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const struct ath11k_hw_ops ipq6018_ops = {
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.get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id,
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.wmi_init_config = ath11k_init_wmi_config_ipq8074,
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.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074,
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.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074,
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};
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const struct ath11k_hw_ops qca6390_ops = {
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.get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
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.wmi_init_config = ath11k_init_wmi_config_qca6390,
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.mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390,
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.mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390,
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};
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#define ATH11K_TX_RING_MASK_0 0x1
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#define ATH11K_TX_RING_MASK_1 0x2
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#define ATH11K_TX_RING_MASK_2 0x4
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#define ATH11K_RX_RING_MASK_0 0x1
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#define ATH11K_RX_RING_MASK_1 0x2
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#define ATH11K_RX_RING_MASK_2 0x4
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#define ATH11K_RX_RING_MASK_3 0x8
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#define ATH11K_RX_ERR_RING_MASK_0 0x1
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#define ATH11K_RX_WBM_REL_RING_MASK_0 0x1
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#define ATH11K_REO_STATUS_RING_MASK_0 0x1
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#define ATH11K_RXDMA2HOST_RING_MASK_0 0x1
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#define ATH11K_RXDMA2HOST_RING_MASK_1 0x2
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#define ATH11K_RXDMA2HOST_RING_MASK_2 0x4
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#define ATH11K_HOST2RXDMA_RING_MASK_0 0x1
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#define ATH11K_HOST2RXDMA_RING_MASK_1 0x2
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#define ATH11K_HOST2RXDMA_RING_MASK_2 0x4
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#define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1
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#define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2
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#define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4
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const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074 = {
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.tx = {
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ATH11K_TX_RING_MASK_0,
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ATH11K_TX_RING_MASK_1,
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ATH11K_TX_RING_MASK_2,
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},
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.rx_mon_status = {
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0, 0, 0, 0,
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ATH11K_RX_MON_STATUS_RING_MASK_0,
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ATH11K_RX_MON_STATUS_RING_MASK_1,
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ATH11K_RX_MON_STATUS_RING_MASK_2,
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},
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.rx = {
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0, 0, 0, 0, 0, 0, 0,
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ATH11K_RX_RING_MASK_0,
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ATH11K_RX_RING_MASK_1,
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ATH11K_RX_RING_MASK_2,
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ATH11K_RX_RING_MASK_3,
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},
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.rx_err = {
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ATH11K_RX_ERR_RING_MASK_0,
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},
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.rx_wbm_rel = {
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ATH11K_RX_WBM_REL_RING_MASK_0,
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},
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.reo_status = {
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ATH11K_REO_STATUS_RING_MASK_0,
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},
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.rxdma2host = {
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ATH11K_RXDMA2HOST_RING_MASK_0,
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ATH11K_RXDMA2HOST_RING_MASK_1,
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ATH11K_RXDMA2HOST_RING_MASK_2,
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},
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.host2rxdma = {
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ATH11K_HOST2RXDMA_RING_MASK_0,
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ATH11K_HOST2RXDMA_RING_MASK_1,
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ATH11K_HOST2RXDMA_RING_MASK_2,
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},
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};
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const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390 = {
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.tx = {
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ATH11K_TX_RING_MASK_0,
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ATH11K_TX_RING_MASK_1,
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ATH11K_TX_RING_MASK_2,
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},
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.rx_mon_status = {
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0, 0, 0, 0,
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ATH11K_RX_MON_STATUS_RING_MASK_0,
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ATH11K_RX_MON_STATUS_RING_MASK_1,
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ATH11K_RX_MON_STATUS_RING_MASK_2,
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},
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.rx = {
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0, 0, 0, 0, 0, 0, 0,
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ATH11K_RX_RING_MASK_0,
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ATH11K_RX_RING_MASK_1,
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ATH11K_RX_RING_MASK_2,
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ATH11K_RX_RING_MASK_3,
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},
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.rx_err = {
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ATH11K_RX_ERR_RING_MASK_0,
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},
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.rx_wbm_rel = {
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ATH11K_RX_WBM_REL_RING_MASK_0,
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},
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.reo_status = {
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ATH11K_REO_STATUS_RING_MASK_0,
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},
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.rxdma2host = {
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ATH11K_RXDMA2HOST_RING_MASK_0,
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ATH11K_RXDMA2HOST_RING_MASK_1,
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ATH11K_RXDMA2HOST_RING_MASK_2,
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},
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.host2rxdma = {
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},
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};
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const struct ath11k_hw_regs ipq8074_regs = {
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/* SW2TCL(x) R0 ring configuration address */
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.hal_tcl1_ring_base_lsb = 0x00000510,
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.hal_tcl1_ring_base_msb = 0x00000514,
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.hal_tcl1_ring_id = 0x00000518,
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.hal_tcl1_ring_misc = 0x00000520,
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.hal_tcl1_ring_tp_addr_lsb = 0x0000052c,
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.hal_tcl1_ring_tp_addr_msb = 0x00000530,
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.hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000540,
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.hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000544,
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.hal_tcl1_ring_msi1_base_lsb = 0x00000558,
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.hal_tcl1_ring_msi1_base_msb = 0x0000055c,
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.hal_tcl1_ring_msi1_data = 0x00000560,
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.hal_tcl2_ring_base_lsb = 0x00000568,
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.hal_tcl_ring_base_lsb = 0x00000618,
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/* TCL STATUS ring address */
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.hal_tcl_status_ring_base_lsb = 0x00000720,
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/* REO2SW(x) R0 ring configuration address */
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.hal_reo1_ring_base_lsb = 0x0000029c,
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.hal_reo1_ring_base_msb = 0x000002a0,
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.hal_reo1_ring_id = 0x000002a4,
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.hal_reo1_ring_misc = 0x000002ac,
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.hal_reo1_ring_hp_addr_lsb = 0x000002b0,
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.hal_reo1_ring_hp_addr_msb = 0x000002b4,
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.hal_reo1_ring_producer_int_setup = 0x000002c0,
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.hal_reo1_ring_msi1_base_lsb = 0x000002e4,
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.hal_reo1_ring_msi1_base_msb = 0x000002e8,
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.hal_reo1_ring_msi1_data = 0x000002ec,
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.hal_reo2_ring_base_lsb = 0x000002f4,
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.hal_reo1_aging_thresh_ix_0 = 0x00000564,
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.hal_reo1_aging_thresh_ix_1 = 0x00000568,
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.hal_reo1_aging_thresh_ix_2 = 0x0000056c,
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.hal_reo1_aging_thresh_ix_3 = 0x00000570,
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/* REO2SW(x) R2 ring pointers (head/tail) address */
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.hal_reo1_ring_hp = 0x00003038,
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.hal_reo1_ring_tp = 0x0000303c,
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.hal_reo2_ring_hp = 0x00003040,
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/* REO2TCL R0 ring configuration address */
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.hal_reo_tcl_ring_base_lsb = 0x000003fc,
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.hal_reo_tcl_ring_hp = 0x00003058,
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/* REO status address */
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.hal_reo_status_ring_base_lsb = 0x00000504,
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.hal_reo_status_hp = 0x00003070,
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};
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const struct ath11k_hw_regs qca6390_regs = {
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/* SW2TCL(x) R0 ring configuration address */
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.hal_tcl1_ring_base_lsb = 0x00000684,
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.hal_tcl1_ring_base_msb = 0x00000688,
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.hal_tcl1_ring_id = 0x0000068c,
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.hal_tcl1_ring_misc = 0x00000694,
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.hal_tcl1_ring_tp_addr_lsb = 0x000006a0,
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.hal_tcl1_ring_tp_addr_msb = 0x000006a4,
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.hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006b4,
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.hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006b8,
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.hal_tcl1_ring_msi1_base_lsb = 0x000006cc,
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.hal_tcl1_ring_msi1_base_msb = 0x000006d0,
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.hal_tcl1_ring_msi1_data = 0x000006d4,
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.hal_tcl2_ring_base_lsb = 0x000006dc,
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.hal_tcl_ring_base_lsb = 0x0000078c,
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/* TCL STATUS ring address */
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.hal_tcl_status_ring_base_lsb = 0x00000894,
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/* REO2SW(x) R0 ring configuration address */
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.hal_reo1_ring_base_lsb = 0x00000244,
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.hal_reo1_ring_base_msb = 0x00000248,
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.hal_reo1_ring_id = 0x0000024c,
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.hal_reo1_ring_misc = 0x00000254,
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.hal_reo1_ring_hp_addr_lsb = 0x00000258,
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.hal_reo1_ring_hp_addr_msb = 0x0000025c,
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.hal_reo1_ring_producer_int_setup = 0x00000268,
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.hal_reo1_ring_msi1_base_lsb = 0x0000028c,
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.hal_reo1_ring_msi1_base_msb = 0x00000290,
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.hal_reo1_ring_msi1_data = 0x00000294,
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.hal_reo2_ring_base_lsb = 0x0000029c,
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.hal_reo1_aging_thresh_ix_0 = 0x0000050c,
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.hal_reo1_aging_thresh_ix_1 = 0x00000510,
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.hal_reo1_aging_thresh_ix_2 = 0x00000514,
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.hal_reo1_aging_thresh_ix_3 = 0x00000518,
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/* REO2SW(x) R2 ring pointers (head/tail) address */
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.hal_reo1_ring_hp = 0x00003030,
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.hal_reo1_ring_tp = 0x00003034,
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.hal_reo2_ring_hp = 0x00003038,
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/* REO2TCL R0 ring configuration address */
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.hal_reo_tcl_ring_base_lsb = 0x000003a4,
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.hal_reo_tcl_ring_hp = 0x00003050,
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/* REO status address */
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.hal_reo_status_ring_base_lsb = 0x000004ac,
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.hal_reo_status_hp = 0x00003068,
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};
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