mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-09-18 22:14:16 +00:00
7ab41c4741
Add the reset controller device of g12a SoC family Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
295 lines
6.6 KiB
Text
295 lines
6.6 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
/*
|
|
* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
|
|
*/
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/clock/g12a-clkc.h>
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
/ {
|
|
compatible = "amlogic,g12a";
|
|
|
|
interrupt-parent = <&gic>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
cpus {
|
|
#address-cells = <0x2>;
|
|
#size-cells = <0x0>;
|
|
|
|
cpu0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x0 0x0>;
|
|
enable-method = "psci";
|
|
next-level-cache = <&l2>;
|
|
};
|
|
|
|
cpu1: cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x0 0x1>;
|
|
enable-method = "psci";
|
|
next-level-cache = <&l2>;
|
|
};
|
|
|
|
cpu2: cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x0 0x2>;
|
|
enable-method = "psci";
|
|
next-level-cache = <&l2>;
|
|
};
|
|
|
|
cpu3: cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x0 0x3>;
|
|
enable-method = "psci";
|
|
next-level-cache = <&l2>;
|
|
};
|
|
|
|
l2: l2-cache0 {
|
|
compatible = "cache";
|
|
};
|
|
};
|
|
|
|
efuse: efuse {
|
|
compatible = "amlogic,meson-gxbb-efuse";
|
|
clocks = <&clkc CLKID_EFUSE>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
read-only;
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
};
|
|
|
|
reserved-memory {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
/* 3 MiB reserved for ARM Trusted Firmware (BL31) */
|
|
secmon_reserved: secmon@5000000 {
|
|
reg = <0x0 0x05000000 0x0 0x300000>;
|
|
no-map;
|
|
};
|
|
};
|
|
|
|
sm: secure-monitor {
|
|
compatible = "amlogic,meson-gxbb-sm";
|
|
};
|
|
|
|
soc {
|
|
compatible = "simple-bus";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
apb: bus@ff600000 {
|
|
compatible = "simple-bus";
|
|
reg = <0x0 0xff600000 0x0 0x200000>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
|
|
|
|
periphs: bus@34400 {
|
|
compatible = "simple-bus";
|
|
reg = <0x0 0x34400 0x0 0x400>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
|
|
|
|
periphs_pinctrl: pinctrl@40 {
|
|
compatible = "amlogic,meson-g12a-periphs-pinctrl";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
gpio: bank@40 {
|
|
reg = <0x0 0x40 0x0 0x4c>,
|
|
<0x0 0xe8 0x0 0x18>,
|
|
<0x0 0x120 0x0 0x18>,
|
|
<0x0 0x2c0 0x0 0x40>,
|
|
<0x0 0x340 0x0 0x1c>;
|
|
reg-names = "gpio",
|
|
"pull",
|
|
"pull-enable",
|
|
"mux",
|
|
"ds";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&periphs_pinctrl 0 0 86>;
|
|
};
|
|
};
|
|
};
|
|
|
|
hiu: bus@3c000 {
|
|
compatible = "simple-bus";
|
|
reg = <0x0 0x3c000 0x0 0x1400>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
|
|
|
|
hhi: system-controller@0 {
|
|
compatible = "amlogic,meson-gx-hhi-sysctrl",
|
|
"simple-mfd", "syscon";
|
|
reg = <0 0 0 0x400>;
|
|
|
|
clkc: clock-controller {
|
|
compatible = "amlogic,g12a-clkc";
|
|
#clock-cells = <1>;
|
|
clocks = <&xtal>;
|
|
clock-names = "xtal";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
aobus: bus@ff800000 {
|
|
compatible = "simple-bus";
|
|
reg = <0x0 0xff800000 0x0 0x100000>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
|
|
|
|
rti: sys-ctrl@0 {
|
|
compatible = "amlogic,meson-gx-ao-sysctrl",
|
|
"simple-mfd", "syscon";
|
|
reg = <0x0 0x0 0x0 0x100>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
|
|
|
|
clkc_AO: clock-controller {
|
|
compatible = "amlogic,meson-g12a-aoclkc";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
clocks = <&xtal>, <&clkc CLKID_CLK81>;
|
|
clock-names = "xtal", "mpeg-clk";
|
|
};
|
|
|
|
ao_pinctrl: pinctrl@14 {
|
|
compatible = "amlogic,meson-g12a-aobus-pinctrl";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
gpio_ao: bank@14 {
|
|
reg = <0x0 0x14 0x0 0x8>,
|
|
<0x0 0x1c 0x0 0x8>,
|
|
<0x0 0x24 0x0 0x14>;
|
|
reg-names = "mux",
|
|
"ds",
|
|
"gpio";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&ao_pinctrl 0 0 15>;
|
|
};
|
|
|
|
uart_ao_a_pins: uart-a-ao {
|
|
mux {
|
|
groups = "uart_ao_a_tx",
|
|
"uart_ao_a_rx";
|
|
function = "uart_ao_a";
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
|
|
mux {
|
|
groups = "uart_ao_a_cts",
|
|
"uart_ao_a_rts";
|
|
function = "uart_ao_a";
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
sec_AO: ao-secure@140 {
|
|
compatible = "amlogic,meson-gx-ao-secure", "syscon";
|
|
reg = <0x0 0x140 0x0 0x140>;
|
|
amlogic,has-chip-id;
|
|
};
|
|
|
|
uart_AO: serial@3000 {
|
|
compatible = "amlogic,meson-gx-uart",
|
|
"amlogic,meson-ao-uart";
|
|
reg = <0x0 0x3000 0x0 0x18>;
|
|
interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&xtal>, <&xtal>, <&xtal>;
|
|
clock-names = "xtal", "pclk", "baud";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart_AO_B: serial@4000 {
|
|
compatible = "amlogic,meson-gx-uart",
|
|
"amlogic,meson-ao-uart";
|
|
reg = <0x0 0x4000 0x0 0x18>;
|
|
interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&xtal>, <&xtal>, <&xtal>;
|
|
clock-names = "xtal", "pclk", "baud";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
gic: interrupt-controller@ffc01000 {
|
|
compatible = "arm,gic-400";
|
|
reg = <0x0 0xffc01000 0 0x1000>,
|
|
<0x0 0xffc02000 0 0x2000>,
|
|
<0x0 0xffc04000 0 0x2000>,
|
|
<0x0 0xffc06000 0 0x2000>;
|
|
interrupt-controller;
|
|
interrupts = <GIC_PPI 9
|
|
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
};
|
|
|
|
cbus: bus@ffd00000 {
|
|
compatible = "simple-bus";
|
|
reg = <0x0 0xffd00000 0x0 0x100000>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
|
|
|
|
reset: reset-controller@1004 {
|
|
compatible = "amlogic,meson-g12a-reset",
|
|
"amlogic,meson-axg-reset";
|
|
reg = <0x0 0x1004 0x0 0x9c>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
clk_msr: clock-measure@18000 {
|
|
compatible = "amlogic,meson-g12a-clk-measure";
|
|
reg = <0x0 0x18000 0x0 0x10>;
|
|
};
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13
|
|
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14
|
|
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11
|
|
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10
|
|
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
|
|
xtal: xtal-clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <24000000>;
|
|
clock-output-names = "xtal";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
};
|