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A number of NAND chips support a feature called on-die ECC, where the NAND chip itself is capable of doing error detection and correction. The new "on-die" value for nand-ecc-mode indicates that we want this functionality to be used. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Richard Weinberger <richard@nod.at> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
70 lines
2.5 KiB
Text
70 lines
2.5 KiB
Text
* NAND chip and NAND controller generic binding
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NAND controller/NAND chip representation:
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The NAND controller should be represented with its own DT node, and all
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NAND chips attached to this controller should be defined as children nodes
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of the NAND controller. This representation should be enforced even for
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simple controllers supporting only one chip.
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Mandatory NAND controller properties:
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- #address-cells: depends on your controller. Should at least be 1 to
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encode the CS line id.
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- #size-cells: depends on your controller. Put zero unless you need a
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mapping between CS lines and dedicated memory regions
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Optional NAND controller properties
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- ranges: only needed if you need to define a mapping between CS lines and
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memory regions
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Optional NAND chip properties:
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- nand-ecc-mode : String, operation mode of the NAND ecc mode.
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Supported values are: "none", "soft", "hw", "hw_syndrome",
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"hw_oob_first", "on-die".
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Deprecated values:
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"soft_bch": use "soft" and nand-ecc-algo instead
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- nand-ecc-algo: string, algorithm of NAND ECC.
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Supported values are: "hamming", "bch".
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- nand-bus-width : 8 or 16 bus width if not present 8
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- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
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- nand-ecc-strength: integer representing the number of bits to correct
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per ECC step.
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- nand-ecc-step-size: integer representing the number of data bytes
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that are covered by a single ECC step.
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- nand-ecc-maximize: boolean used to specify that you want to maximize ECC
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strength. The maximum ECC strength is both controller and
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chip dependent. The controller side has to select the ECC
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config providing the best strength and taking the OOB area
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size constraint into account.
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This is particularly useful when only the in-band area is
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used by the upper layers, and you want to make your NAND
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as reliable as possible.
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The ECC strength and ECC step size properties define the correction capability
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of a controller. Together, they say a controller can correct "{strength} bit
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errors per {size} bytes".
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The interpretation of these parameters is implementation-defined, so not all
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implementations must support all possible combinations. However, implementations
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are encouraged to further specify the value(s) they support.
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Example:
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nand-controller {
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#address-cells = <1>;
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#size-cells = <0>;
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/* controller specific properties */
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nand@0 {
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reg = <0>;
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nand-ecc-mode = "soft";
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nand-ecc-algo = "bch";
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/* controller specific properties */
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};
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};
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