Jaehyun Chung 785908cf19 drm/amd/display: OTC underflow fix ... [Why] Underflow occurs on some display setups(repro'd on 3x4K HDR) on boot, mode set, and hot-plugs with. Underflow occurs because mem clk is not set high after disabling pstate switching. This behaviour occurs because some calculations assumed displays were synchronized. [How] Add a condition to check if timing sync is disabled so that synchronized vblank can be set to false. Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-09-13 18:03:06 -05:00
..
amdgpu_dm	drm/amd/display: update navi to use new surface programming behaviour	2019-09-13 18:01:09 -05:00
dc	drm/amd/display: OTC underflow fix	2019-09-13 18:03:06 -05:00
include	drm/amd/display: add dal_asic_id for renoir	2019-08-29 15:52:33 -05:00
modules	drm/amd/display: remove unused function setFieldWithMask	2019-08-27 10:09:12 -05:00
Kconfig	drm/amd/display: add Renoir to kconfig	2019-08-29 15:52:33 -05:00
Makefile	drm/amd/display: move clk_mgr files to right place	2019-05-31 10:39:31 -05:00
TODO