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7632b30e4b
The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
103 lines
2.8 KiB
C
103 lines
2.8 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <subdev/clk.h>
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#include "pll.h"
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#include <subdev/bios.h>
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#include <subdev/bios/pll.h>
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#include <subdev/devinit/nv04.h>
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struct nv04_clk_priv {
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struct nvkm_clk base;
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};
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int
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nv04_clk_pll_calc(struct nvkm_clk *clock, struct nvbios_pll *info,
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int clk, struct nvkm_pll_vals *pv)
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{
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int N1, M1, N2, M2, P;
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int ret = nv04_pll_calc(nv_subdev(clock), info, clk, &N1, &M1, &N2, &M2, &P);
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if (ret) {
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pv->refclk = info->refclk;
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pv->N1 = N1;
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pv->M1 = M1;
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pv->N2 = N2;
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pv->M2 = M2;
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pv->log2P = P;
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}
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return ret;
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}
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int
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nv04_clk_pll_prog(struct nvkm_clk *clk, u32 reg1, struct nvkm_pll_vals *pv)
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{
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struct nvkm_devinit *devinit = nvkm_devinit(clk);
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int cv = nvkm_bios(clk)->version.chip;
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if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
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cv >= 0x40) {
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if (reg1 > 0x405c)
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setPLL_double_highregs(devinit, reg1, pv);
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else
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setPLL_double_lowregs(devinit, reg1, pv);
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} else
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setPLL_single(devinit, reg1, pv);
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return 0;
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}
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static struct nvkm_domain
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nv04_domain[] = {
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{ nv_clk_src_max }
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};
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static int
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nv04_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct nv04_clk_priv *priv;
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int ret;
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ret = nvkm_clk_create(parent, engine, oclass, nv04_domain,
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NULL, 0, false, &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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priv->base.pll_calc = nv04_clk_pll_calc;
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priv->base.pll_prog = nv04_clk_pll_prog;
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return 0;
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}
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struct nvkm_oclass
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nv04_clk_oclass = {
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.handle = NV_SUBDEV(CLK, 0x04),
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.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = nv04_clk_ctor,
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.dtor = _nvkm_clk_dtor,
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.init = _nvkm_clk_init,
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.fini = _nvkm_clk_fini,
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},
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};
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