linux/arch/arc/include/asm
Vineet Gupta 72d7288061 ARCv2: SMP: clocksource: Enable Global Real Time counter
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-22 14:06:57 +05:30
..
arcregs.h ARCv2: MMUv4: cache programming model changes 2015-06-22 14:06:55 +05:30
asm-offsets.h
atomic.h ARC: unbork !LLSC build 2015-05-10 12:06:57 +05:30
bitops.h ARCv2: Support for ARCv2 ISA and HS38x cores 2015-06-22 14:06:55 +05:30
bug.h
cache.h ARCv2: MMUv4: support aliasing icache config 2015-06-22 14:06:56 +05:30
cacheflush.h ARC: fold ___flush_dcache_page into __flush_dcache_page 2015-05-19 11:27:13 +05:30
checksum.h
clk.h
cmpxchg.h
current.h
delay.h ARCv2: Adhere to Zero Delay loop restriction 2015-06-22 14:06:56 +05:30
disasm.h
dma-mapping.h ARC: remove the unused platform helpers from dma mapping API 2015-06-19 18:09:23 +05:30
dma.h
elf.h ARCv2: Support for ARCv2 ISA and HS38x cores 2015-06-22 14:06:55 +05:30
entry-arcv2.h ARCv2: Support for ARCv2 ISA and HS38x cores 2015-06-22 14:06:55 +05:30
entry-compact.h ARC: intc: split into ARCompact ISA specific, common bits 2015-06-19 18:09:40 +05:30
entry.h ARCv2: STAR 9000808988: signals involving Delay Slot 2015-06-22 14:06:55 +05:30
exec.h
futex.h
io.h
irq.h ARCv2: SMP: Support ARConnect (MCIP) for Inter-Core-Interrupts et al 2015-06-22 14:06:56 +05:30
irqflags-arcv2.h ARCv2: STAR 9000814690: Really Re-enable interrupts to avoid deadlocks 2015-06-22 14:06:55 +05:30
irqflags-compact.h ARCv2: Support for ARCv2 ISA and HS38x cores 2015-06-22 14:06:55 +05:30
irqflags.h ARCv2: Support for ARCv2 ISA and HS38x cores 2015-06-22 14:06:55 +05:30
Kbuild
kdebug.h
kgdb.h
kprobes.h
linkage.h
mach_desc.h
mcip.h ARCv2: SMP: clocksource: Enable Global Real Time counter 2015-06-22 14:06:57 +05:30
mmu.h ARCv2: MMUv4: TLB programming Model changes 2015-06-22 14:06:55 +05:30
mmu_context.h
module.h
mutex.h
page.h
perf_event.h ARC: perf: support cache hit/miss ratio 2015-04-20 18:27:34 +05:30
pgalloc.h
pgtable.h ARCv2: MMUv4: TLB programming Model changes 2015-06-22 14:06:55 +05:30
processor.h ARC: mm: document system mem map clearly 2015-06-19 18:09:29 +05:30
ptrace.h ARCv2: Support for ARCv2 ISA and HS38x cores 2015-06-22 14:06:55 +05:30
sections.h
segment.h
serial.h ARC: Dynamically determine BASE_BAUD from DeviceTree 2015-02-02 17:08:37 +05:30
setup.h
shmparam.h
smp.h
spinlock.h
spinlock_types.h
stacktrace.h ARC: Make arc_unwind_core accessible externally 2015-02-27 10:15:00 +05:30
string.h
switch_to.h
syscall.h
syscalls.h
thread_info.h ARCv2: Support for ARCv2 ISA and HS38x cores 2015-06-22 14:06:55 +05:30
timex.h
tlb-mmu1.h
tlb.h
tlbflush.h
uaccess.h ARCv2: Adhere to Zero Delay loop restriction 2015-06-22 14:06:56 +05:30
unaligned.h
unwind.h