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91c960b005
A subsequent patch will add additional atomic operations. These new operations will use the same opcode field as the existing XADD, with the immediate discriminating different operations. In preparation, rename the instruction mode BPF_ATOMIC and start calling the zero immediate BPF_ADD. This is possible (doesn't break existing valid BPF progs) because the immediate field is currently reserved MBZ and BPF_ADD is zero. All uses are removed from the tree but the BPF_XADD definition is kept around to avoid breaking builds for people including kernel headers. Signed-off-by: Brendan Jackman <jackmanb@google.com> Signed-off-by: Alexei Starovoitov <ast@kernel.org> Acked-by: Björn Töpel <bjorn.topel@gmail.com> Link: https://lore.kernel.org/bpf/20210114181751.768687-5-jackmanb@google.com
217 lines
5.4 KiB
C
217 lines
5.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* eBPF instruction mini library */
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#ifndef __BPF_INSN_H
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#define __BPF_INSN_H
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struct bpf_insn;
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/* ALU ops on registers, bpf_add|sub|...: dst_reg += src_reg */
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#define BPF_ALU64_REG(OP, DST, SRC) \
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((struct bpf_insn) { \
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.code = BPF_ALU64 | BPF_OP(OP) | BPF_X, \
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.dst_reg = DST, \
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.src_reg = SRC, \
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.off = 0, \
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.imm = 0 })
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#define BPF_ALU32_REG(OP, DST, SRC) \
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((struct bpf_insn) { \
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.code = BPF_ALU | BPF_OP(OP) | BPF_X, \
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.dst_reg = DST, \
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.src_reg = SRC, \
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.off = 0, \
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.imm = 0 })
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/* ALU ops on immediates, bpf_add|sub|...: dst_reg += imm32 */
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#define BPF_ALU64_IMM(OP, DST, IMM) \
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((struct bpf_insn) { \
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.code = BPF_ALU64 | BPF_OP(OP) | BPF_K, \
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.dst_reg = DST, \
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.src_reg = 0, \
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.off = 0, \
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.imm = IMM })
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#define BPF_ALU32_IMM(OP, DST, IMM) \
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((struct bpf_insn) { \
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.code = BPF_ALU | BPF_OP(OP) | BPF_K, \
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.dst_reg = DST, \
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.src_reg = 0, \
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.off = 0, \
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.imm = IMM })
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/* Short form of mov, dst_reg = src_reg */
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#define BPF_MOV64_REG(DST, SRC) \
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((struct bpf_insn) { \
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.code = BPF_ALU64 | BPF_MOV | BPF_X, \
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.dst_reg = DST, \
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.src_reg = SRC, \
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.off = 0, \
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.imm = 0 })
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#define BPF_MOV32_REG(DST, SRC) \
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((struct bpf_insn) { \
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.code = BPF_ALU | BPF_MOV | BPF_X, \
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.dst_reg = DST, \
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.src_reg = SRC, \
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.off = 0, \
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.imm = 0 })
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/* Short form of mov, dst_reg = imm32 */
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#define BPF_MOV64_IMM(DST, IMM) \
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((struct bpf_insn) { \
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.code = BPF_ALU64 | BPF_MOV | BPF_K, \
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.dst_reg = DST, \
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.src_reg = 0, \
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.off = 0, \
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.imm = IMM })
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#define BPF_MOV32_IMM(DST, IMM) \
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((struct bpf_insn) { \
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.code = BPF_ALU | BPF_MOV | BPF_K, \
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.dst_reg = DST, \
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.src_reg = 0, \
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.off = 0, \
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.imm = IMM })
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/* BPF_LD_IMM64 macro encodes single 'load 64-bit immediate' insn */
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#define BPF_LD_IMM64(DST, IMM) \
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BPF_LD_IMM64_RAW(DST, 0, IMM)
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#define BPF_LD_IMM64_RAW(DST, SRC, IMM) \
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((struct bpf_insn) { \
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.code = BPF_LD | BPF_DW | BPF_IMM, \
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.dst_reg = DST, \
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.src_reg = SRC, \
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.off = 0, \
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.imm = (__u32) (IMM) }), \
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((struct bpf_insn) { \
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.code = 0, /* zero is reserved opcode */ \
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.dst_reg = 0, \
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.src_reg = 0, \
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.off = 0, \
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.imm = ((__u64) (IMM)) >> 32 })
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#ifndef BPF_PSEUDO_MAP_FD
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# define BPF_PSEUDO_MAP_FD 1
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#endif
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/* pseudo BPF_LD_IMM64 insn used to refer to process-local map_fd */
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#define BPF_LD_MAP_FD(DST, MAP_FD) \
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BPF_LD_IMM64_RAW(DST, BPF_PSEUDO_MAP_FD, MAP_FD)
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/* Direct packet access, R0 = *(uint *) (skb->data + imm32) */
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#define BPF_LD_ABS(SIZE, IMM) \
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((struct bpf_insn) { \
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.code = BPF_LD | BPF_SIZE(SIZE) | BPF_ABS, \
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.dst_reg = 0, \
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.src_reg = 0, \
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.off = 0, \
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.imm = IMM })
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/* Memory load, dst_reg = *(uint *) (src_reg + off16) */
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#define BPF_LDX_MEM(SIZE, DST, SRC, OFF) \
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((struct bpf_insn) { \
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.code = BPF_LDX | BPF_SIZE(SIZE) | BPF_MEM, \
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.dst_reg = DST, \
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.src_reg = SRC, \
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.off = OFF, \
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.imm = 0 })
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/* Memory store, *(uint *) (dst_reg + off16) = src_reg */
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#define BPF_STX_MEM(SIZE, DST, SRC, OFF) \
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((struct bpf_insn) { \
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.code = BPF_STX | BPF_SIZE(SIZE) | BPF_MEM, \
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.dst_reg = DST, \
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.src_reg = SRC, \
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.off = OFF, \
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.imm = 0 })
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/* Atomic memory add, *(uint *)(dst_reg + off16) += src_reg */
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#define BPF_STX_XADD(SIZE, DST, SRC, OFF) \
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((struct bpf_insn) { \
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.code = BPF_STX | BPF_SIZE(SIZE) | BPF_ATOMIC, \
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.dst_reg = DST, \
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.src_reg = SRC, \
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.off = OFF, \
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.imm = BPF_ADD })
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/* Memory store, *(uint *) (dst_reg + off16) = imm32 */
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#define BPF_ST_MEM(SIZE, DST, OFF, IMM) \
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((struct bpf_insn) { \
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.code = BPF_ST | BPF_SIZE(SIZE) | BPF_MEM, \
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.dst_reg = DST, \
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.src_reg = 0, \
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.off = OFF, \
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.imm = IMM })
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/* Conditional jumps against registers, if (dst_reg 'op' src_reg) goto pc + off16 */
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#define BPF_JMP_REG(OP, DST, SRC, OFF) \
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((struct bpf_insn) { \
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.code = BPF_JMP | BPF_OP(OP) | BPF_X, \
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.dst_reg = DST, \
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.src_reg = SRC, \
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.off = OFF, \
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.imm = 0 })
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/* Like BPF_JMP_REG, but with 32-bit wide operands for comparison. */
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#define BPF_JMP32_REG(OP, DST, SRC, OFF) \
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((struct bpf_insn) { \
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.code = BPF_JMP32 | BPF_OP(OP) | BPF_X, \
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.dst_reg = DST, \
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.src_reg = SRC, \
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.off = OFF, \
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.imm = 0 })
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/* Conditional jumps against immediates, if (dst_reg 'op' imm32) goto pc + off16 */
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#define BPF_JMP_IMM(OP, DST, IMM, OFF) \
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((struct bpf_insn) { \
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.code = BPF_JMP | BPF_OP(OP) | BPF_K, \
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.dst_reg = DST, \
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.src_reg = 0, \
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.off = OFF, \
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.imm = IMM })
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/* Like BPF_JMP_IMM, but with 32-bit wide operands for comparison. */
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#define BPF_JMP32_IMM(OP, DST, IMM, OFF) \
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((struct bpf_insn) { \
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.code = BPF_JMP32 | BPF_OP(OP) | BPF_K, \
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.dst_reg = DST, \
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.src_reg = 0, \
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.off = OFF, \
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.imm = IMM })
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/* Raw code statement block */
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#define BPF_RAW_INSN(CODE, DST, SRC, OFF, IMM) \
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((struct bpf_insn) { \
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.code = CODE, \
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.dst_reg = DST, \
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.src_reg = SRC, \
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.off = OFF, \
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.imm = IMM })
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/* Program exit */
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#define BPF_EXIT_INSN() \
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((struct bpf_insn) { \
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.code = BPF_JMP | BPF_EXIT, \
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.dst_reg = 0, \
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.src_reg = 0, \
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.off = 0, \
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.imm = 0 })
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#endif
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