Conor Dooley 6fc655ed49 riscv: dts: microchip: icicle: update pci address properties ... For the v2022.09 reference design the PCI root port's data region has been moved to FIC1 from FIC0. This is a shorter path, allowing for higher clock rates and improved through-put. As a result, the address at which the PCIe's data region appears to the core complex has changed. The config region's address is unchanged. As FIC0 is no longer used, its clock can be removed too. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>		2022-09-27 18:53:58 +01:00
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Makefile	riscv: dts: microchip: add the sundance polarberry	2022-06-01 15:28:29 -07:00
mpfs-icicle-kit-fabric.dtsi	riscv: dts: microchip: icicle: update pci address properties	2022-09-27 18:53:58 +01:00
mpfs-icicle-kit.dts	riscv: dts: microchip: add pci dma ranges for the icicle kit	2022-09-27 18:53:58 +01:00
mpfs-polarberry-fabric.dtsi	riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi	2022-09-27 18:53:58 +01:00
mpfs-polarberry.dts	riscv: dts: microchip: add the sundance polarberry	2022-06-01 15:28:29 -07:00
mpfs.dtsi	riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi	2022-09-27 18:53:58 +01:00