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c852ac8044
Since the iop32x code isn't iop321-specific, and the iop33x code isn't iop331-specfic, do a s/iop321/iop32x/ and s/iop331/iop33x/, and tidy up the code to conform to the coding style guidelines somewhat better. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
443 lines
10 KiB
C
443 lines
10 KiB
C
/**
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* @file op_model_xscale.c
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* XScale Performance Monitor Driver
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*
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* @remark Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com>
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* @remark Copyright 2000-2004 MontaVista Software Inc
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* @remark Copyright 2004 Dave Jiang <dave.jiang@intel.com>
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* @remark Copyright 2004 Intel Corporation
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* @remark Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk>
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* @remark Copyright 2004 OProfile Authors
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*
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* @remark Read the file COPYING
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*
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* @author Zwane Mwaikambo
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*/
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/* #define DEBUG */
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/oprofile.h>
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#include <linux/interrupt.h>
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#include <asm/irq.h>
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#include <asm/system.h>
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#include "op_counter.h"
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#include "op_arm_model.h"
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#define PMU_ENABLE 0x001 /* Enable counters */
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#define PMN_RESET 0x002 /* Reset event counters */
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#define CCNT_RESET 0x004 /* Reset clock counter */
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#define PMU_RESET (CCNT_RESET | PMN_RESET)
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#define PMU_CNT64 0x008 /* Make CCNT count every 64th cycle */
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/* TODO do runtime detection */
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#ifdef CONFIG_ARCH_IOP310
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#define XSCALE_PMU_IRQ IRQ_XS80200_PMU
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#endif
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#ifdef CONFIG_ARCH_IOP32X
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#define XSCALE_PMU_IRQ IRQ_IOP32X_CORE_PMU
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#endif
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#ifdef CONFIG_ARCH_IOP33X
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#define XSCALE_PMU_IRQ IRQ_IOP33X_CORE_PMU
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#endif
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#ifdef CONFIG_ARCH_PXA
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#define XSCALE_PMU_IRQ IRQ_PMU
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#endif
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/*
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* Different types of events that can be counted by the XScale PMU
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* as used by Oprofile userspace. Here primarily for documentation
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* purposes.
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*/
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#define EVT_ICACHE_MISS 0x00
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#define EVT_ICACHE_NO_DELIVER 0x01
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#define EVT_DATA_STALL 0x02
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#define EVT_ITLB_MISS 0x03
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#define EVT_DTLB_MISS 0x04
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#define EVT_BRANCH 0x05
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#define EVT_BRANCH_MISS 0x06
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#define EVT_INSTRUCTION 0x07
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#define EVT_DCACHE_FULL_STALL 0x08
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#define EVT_DCACHE_FULL_STALL_CONTIG 0x09
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#define EVT_DCACHE_ACCESS 0x0A
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#define EVT_DCACHE_MISS 0x0B
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#define EVT_DCACE_WRITE_BACK 0x0C
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#define EVT_PC_CHANGED 0x0D
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#define EVT_BCU_REQUEST 0x10
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#define EVT_BCU_FULL 0x11
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#define EVT_BCU_DRAIN 0x12
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#define EVT_BCU_ECC_NO_ELOG 0x14
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#define EVT_BCU_1_BIT_ERR 0x15
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#define EVT_RMW 0x16
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/* EVT_CCNT is not hardware defined */
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#define EVT_CCNT 0xFE
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#define EVT_UNUSED 0xFF
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struct pmu_counter {
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volatile unsigned long ovf;
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unsigned long reset_counter;
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};
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enum { CCNT, PMN0, PMN1, PMN2, PMN3, MAX_COUNTERS };
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static struct pmu_counter results[MAX_COUNTERS];
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/*
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* There are two versions of the PMU in current XScale processors
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* with differing register layouts and number of performance counters.
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* e.g. IOP32x is xsc1 whilst IOP33x is xsc2.
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* We detect which register layout to use in xscale_detect_pmu()
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*/
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enum { PMU_XSC1, PMU_XSC2 };
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struct pmu_type {
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int id;
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char *name;
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int num_counters;
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unsigned int int_enable;
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unsigned int cnt_ovf[MAX_COUNTERS];
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unsigned int int_mask[MAX_COUNTERS];
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};
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static struct pmu_type pmu_parms[] = {
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{
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.id = PMU_XSC1,
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.name = "arm/xscale1",
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.num_counters = 3,
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.int_mask = { [PMN0] = 0x10, [PMN1] = 0x20,
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[CCNT] = 0x40 },
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.cnt_ovf = { [CCNT] = 0x400, [PMN0] = 0x100,
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[PMN1] = 0x200},
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},
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{
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.id = PMU_XSC2,
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.name = "arm/xscale2",
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.num_counters = 5,
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.int_mask = { [CCNT] = 0x01, [PMN0] = 0x02,
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[PMN1] = 0x04, [PMN2] = 0x08,
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[PMN3] = 0x10 },
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.cnt_ovf = { [CCNT] = 0x01, [PMN0] = 0x02,
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[PMN1] = 0x04, [PMN2] = 0x08,
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[PMN3] = 0x10 },
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},
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};
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static struct pmu_type *pmu;
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static void write_pmnc(u32 val)
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{
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if (pmu->id == PMU_XSC1) {
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/* upper 4bits and 7, 11 are write-as-0 */
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val &= 0xffff77f;
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__asm__ __volatile__ ("mcr p14, 0, %0, c0, c0, 0" : : "r" (val));
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} else {
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/* bits 4-23 are write-as-0, 24-31 are write ignored */
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val &= 0xf;
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__asm__ __volatile__ ("mcr p14, 0, %0, c0, c1, 0" : : "r" (val));
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}
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}
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static u32 read_pmnc(void)
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{
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u32 val;
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if (pmu->id == PMU_XSC1)
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__asm__ __volatile__ ("mrc p14, 0, %0, c0, c0, 0" : "=r" (val));
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else {
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__asm__ __volatile__ ("mrc p14, 0, %0, c0, c1, 0" : "=r" (val));
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/* bits 1-2 and 4-23 are read-unpredictable */
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val &= 0xff000009;
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}
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return val;
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}
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static u32 __xsc1_read_counter(int counter)
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{
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u32 val = 0;
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switch (counter) {
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case CCNT:
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__asm__ __volatile__ ("mrc p14, 0, %0, c1, c0, 0" : "=r" (val));
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break;
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case PMN0:
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__asm__ __volatile__ ("mrc p14, 0, %0, c2, c0, 0" : "=r" (val));
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break;
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case PMN1:
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__asm__ __volatile__ ("mrc p14, 0, %0, c3, c0, 0" : "=r" (val));
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break;
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}
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return val;
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}
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static u32 __xsc2_read_counter(int counter)
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{
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u32 val = 0;
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switch (counter) {
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case CCNT:
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__asm__ __volatile__ ("mrc p14, 0, %0, c1, c1, 0" : "=r" (val));
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break;
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case PMN0:
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__asm__ __volatile__ ("mrc p14, 0, %0, c0, c2, 0" : "=r" (val));
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break;
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case PMN1:
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__asm__ __volatile__ ("mrc p14, 0, %0, c1, c2, 0" : "=r" (val));
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break;
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case PMN2:
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__asm__ __volatile__ ("mrc p14, 0, %0, c2, c2, 0" : "=r" (val));
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break;
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case PMN3:
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__asm__ __volatile__ ("mrc p14, 0, %0, c3, c2, 0" : "=r" (val));
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break;
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}
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return val;
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}
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static u32 read_counter(int counter)
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{
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u32 val;
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if (pmu->id == PMU_XSC1)
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val = __xsc1_read_counter(counter);
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else
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val = __xsc2_read_counter(counter);
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return val;
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}
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static void __xsc1_write_counter(int counter, u32 val)
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{
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switch (counter) {
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case CCNT:
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__asm__ __volatile__ ("mcr p14, 0, %0, c1, c0, 0" : : "r" (val));
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break;
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case PMN0:
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__asm__ __volatile__ ("mcr p14, 0, %0, c2, c0, 0" : : "r" (val));
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break;
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case PMN1:
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__asm__ __volatile__ ("mcr p14, 0, %0, c3, c0, 0" : : "r" (val));
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break;
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}
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}
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static void __xsc2_write_counter(int counter, u32 val)
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{
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switch (counter) {
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case CCNT:
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__asm__ __volatile__ ("mcr p14, 0, %0, c1, c1, 0" : : "r" (val));
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break;
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case PMN0:
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__asm__ __volatile__ ("mcr p14, 0, %0, c0, c2, 0" : : "r" (val));
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break;
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case PMN1:
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__asm__ __volatile__ ("mcr p14, 0, %0, c1, c2, 0" : : "r" (val));
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break;
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case PMN2:
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__asm__ __volatile__ ("mcr p14, 0, %0, c2, c2, 0" : : "r" (val));
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break;
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case PMN3:
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__asm__ __volatile__ ("mcr p14, 0, %0, c3, c2, 0" : : "r" (val));
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break;
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}
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}
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static void write_counter(int counter, u32 val)
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{
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if (pmu->id == PMU_XSC1)
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__xsc1_write_counter(counter, val);
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else
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__xsc2_write_counter(counter, val);
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}
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static int xscale_setup_ctrs(void)
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{
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u32 evtsel, pmnc;
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int i;
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for (i = CCNT; i < MAX_COUNTERS; i++) {
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if (counter_config[i].enabled)
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continue;
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counter_config[i].event = EVT_UNUSED;
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}
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switch (pmu->id) {
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case PMU_XSC1:
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pmnc = (counter_config[PMN1].event << 20) | (counter_config[PMN0].event << 12);
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pr_debug("xscale_setup_ctrs: pmnc: %#08x\n", pmnc);
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write_pmnc(pmnc);
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break;
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case PMU_XSC2:
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evtsel = counter_config[PMN0].event | (counter_config[PMN1].event << 8) |
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(counter_config[PMN2].event << 16) | (counter_config[PMN3].event << 24);
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pr_debug("xscale_setup_ctrs: evtsel %#08x\n", evtsel);
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__asm__ __volatile__ ("mcr p14, 0, %0, c8, c1, 0" : : "r" (evtsel));
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break;
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}
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for (i = CCNT; i < MAX_COUNTERS; i++) {
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if (counter_config[i].event == EVT_UNUSED) {
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counter_config[i].event = 0;
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pmu->int_enable &= ~pmu->int_mask[i];
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continue;
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}
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results[i].reset_counter = counter_config[i].count;
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write_counter(i, -(u32)counter_config[i].count);
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pmu->int_enable |= pmu->int_mask[i];
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pr_debug("xscale_setup_ctrs: counter%d %#08x from %#08lx\n", i,
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read_counter(i), counter_config[i].count);
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}
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return 0;
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}
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static void inline __xsc1_check_ctrs(void)
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{
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int i;
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u32 pmnc = read_pmnc();
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/* NOTE: there's an A stepping errata that states if an overflow */
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/* bit already exists and another occurs, the previous */
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/* Overflow bit gets cleared. There's no workaround. */
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/* Fixed in B stepping or later */
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/* Write the value back to clear the overflow flags. Overflow */
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/* flags remain in pmnc for use below */
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write_pmnc(pmnc & ~PMU_ENABLE);
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for (i = CCNT; i <= PMN1; i++) {
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if (!(pmu->int_mask[i] & pmu->int_enable))
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continue;
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if (pmnc & pmu->cnt_ovf[i])
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results[i].ovf++;
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}
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}
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static void inline __xsc2_check_ctrs(void)
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{
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int i;
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u32 flag = 0, pmnc = read_pmnc();
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pmnc &= ~PMU_ENABLE;
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write_pmnc(pmnc);
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/* read overflow flag register */
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__asm__ __volatile__ ("mrc p14, 0, %0, c5, c1, 0" : "=r" (flag));
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for (i = CCNT; i <= PMN3; i++) {
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if (!(pmu->int_mask[i] & pmu->int_enable))
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continue;
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if (flag & pmu->cnt_ovf[i])
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results[i].ovf++;
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}
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/* writeback clears overflow bits */
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__asm__ __volatile__ ("mcr p14, 0, %0, c5, c1, 0" : : "r" (flag));
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}
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static irqreturn_t xscale_pmu_interrupt(int irq, void *arg, struct pt_regs *regs)
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{
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int i;
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u32 pmnc;
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if (pmu->id == PMU_XSC1)
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__xsc1_check_ctrs();
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else
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__xsc2_check_ctrs();
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for (i = CCNT; i < MAX_COUNTERS; i++) {
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if (!results[i].ovf)
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continue;
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write_counter(i, -(u32)results[i].reset_counter);
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oprofile_add_sample(regs, i);
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results[i].ovf--;
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}
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pmnc = read_pmnc() | PMU_ENABLE;
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write_pmnc(pmnc);
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return IRQ_HANDLED;
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}
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static void xscale_pmu_stop(void)
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{
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u32 pmnc = read_pmnc();
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pmnc &= ~PMU_ENABLE;
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write_pmnc(pmnc);
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free_irq(XSCALE_PMU_IRQ, results);
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}
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static int xscale_pmu_start(void)
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{
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int ret;
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u32 pmnc = read_pmnc();
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ret = request_irq(XSCALE_PMU_IRQ, xscale_pmu_interrupt, IRQF_DISABLED,
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"XScale PMU", (void *)results);
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if (ret < 0) {
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printk(KERN_ERR "oprofile: unable to request IRQ%d for XScale PMU\n",
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XSCALE_PMU_IRQ);
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return ret;
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}
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if (pmu->id == PMU_XSC1)
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pmnc |= pmu->int_enable;
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else {
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__asm__ __volatile__ ("mcr p14, 0, %0, c4, c1, 0" : : "r" (pmu->int_enable));
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pmnc &= ~PMU_CNT64;
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}
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pmnc |= PMU_ENABLE;
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write_pmnc(pmnc);
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pr_debug("xscale_pmu_start: pmnc: %#08x mask: %08x\n", pmnc, pmu->int_enable);
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return 0;
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}
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static int xscale_detect_pmu(void)
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{
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int ret = 0;
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u32 id;
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id = (read_cpuid(CPUID_ID) >> 13) & 0x7;
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switch (id) {
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case 1:
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pmu = &pmu_parms[PMU_XSC1];
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break;
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case 2:
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pmu = &pmu_parms[PMU_XSC2];
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break;
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default:
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ret = -ENODEV;
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break;
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}
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if (!ret) {
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op_xscale_spec.name = pmu->name;
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op_xscale_spec.num_counters = pmu->num_counters;
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pr_debug("xscale_detect_pmu: detected %s PMU\n", pmu->name);
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}
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return ret;
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}
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struct op_arm_model_spec op_xscale_spec = {
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.init = xscale_detect_pmu,
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.setup_ctrs = xscale_setup_ctrs,
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.start = xscale_pmu_start,
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.stop = xscale_pmu_stop,
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};
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