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67c9845bea
This patch adds initial support for using the MPU, which is necessary for SMP operation on PMSAv7 processors because it is the only way to ensure memory is shared. This is an initial patch and full SMP support is added later in this series. The setup of the MPU is performed in a way analagous to that for the MMU: Very early initialisation before the C environment is brought up, followed by a sanity check and more complete initialisation in C. This patch provides the simplest possible memory region configuration: MPU_PROBE_REGION: Reserved for probing MPU details, not enabled MPU_BG_REGION: A 'background' region that specifies all memory strongly ordered MPU_RAM_REGION: A single shared, cacheable, normal region for the valid RAM. In this early initialisation code we simply map the whole of the address space with the BG_REGION and (at least) the kernel with the RAM_REGION. The MPU has region alignment constraints that require us to round past the end of the kernel. As region 2 has a higher priority than region 1, it overrides the strongly- ordered behaviour for RAM only. Subsequent patches will add more complete initialisation from the C-world and support for bringing up secondary CPUs. Signed-off-by: Jonathan Austin <jonathan.austin@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> CC: Hyok S. Choi <hyok.choi@samsung.com>
75 lines
1.7 KiB
C
75 lines
1.7 KiB
C
#ifndef __ARM_MPU_H
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#define __ARM_MPU_H
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#ifdef CONFIG_ARM_MPU
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/* MPUIR layout */
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#define MPUIR_nU 1
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#define MPUIR_DREGION 8
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#define MPUIR_IREGION 16
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#define MPUIR_DREGION_SZMASK (0xFF << MPUIR_DREGION)
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#define MPUIR_IREGION_SZMASK (0xFF << MPUIR_IREGION)
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/* ID_MMFR0 data relevant to MPU */
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#define MMFR0_PMSA (0xF << 4)
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#define MMFR0_PMSAv7 (3 << 4)
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/* MPU D/I Size Register fields */
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#define MPU_RSR_SZ 1
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#define MPU_RSR_EN 0
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/* The D/I RSR value for an enabled region spanning the whole of memory */
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#define MPU_RSR_ALL_MEM 63
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/* Individual bits in the DR/IR ACR */
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#define MPU_ACR_XN (1 << 12)
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#define MPU_ACR_SHARED (1 << 2)
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/* C, B and TEX[2:0] bits only have semantic meanings when grouped */
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#define MPU_RGN_CACHEABLE 0xB
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#define MPU_RGN_SHARED_CACHEABLE (MPU_RGN_CACHEABLE | MPU_ACR_SHARED)
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#define MPU_RGN_STRONGLY_ORDERED 0
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/* Main region should only be shared for SMP */
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#ifdef CONFIG_SMP
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#define MPU_RGN_NORMAL (MPU_RGN_CACHEABLE | MPU_ACR_SHARED)
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#else
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#define MPU_RGN_NORMAL MPU_RGN_CACHEABLE
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#endif
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/* Access permission bits of ACR (only define those that we use)*/
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#define MPU_AP_PL1RW_PL0RW (0x3 << 8)
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#define MPU_AP_PL1RW_PL0R0 (0x2 << 8)
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#define MPU_AP_PL1RW_PL0NA (0x1 << 8)
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/* For minimal static MPU region configurations */
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#define MPU_PROBE_REGION 0
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#define MPU_BG_REGION 1
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#define MPU_RAM_REGION 2
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/* Maximum number of regions Linux is interested in */
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#define MPU_MAX_REGIONS 16
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#define MPU_DATA_SIDE 0
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#define MPU_INSTR_SIDE 1
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#ifndef __ASSEMBLY__
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struct mpu_rgn {
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/* Assume same attributes for d/i-side */
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u32 drbar;
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u32 drsr;
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u32 dracr;
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};
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struct mpu_rgn_info {
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u32 mpuir;
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struct mpu_rgn rgns[MPU_MAX_REGIONS];
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};
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extern struct mpu_rgn_info mpu_rgn_info;
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#endif /* __ASSEMBLY__ */
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#endif /* CONFIG_ARM_MPU */
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#endif
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