linux/drivers/net/ethernet/chelsio/inline_crypto
Rohit Maheshwari 63ee4591fa ch_ktls: Correction in middle record handling
If a record starts in middle, reset TCB UNA so that we could
avoid sending out extra packet which is needed to make it 16
byte aligned to start AES CTR.
Check also considers prev_seq, which should be what is
actually sent, not the skb data length.
Avoid updating partial TAG to HW at any point of time, that's
why we need to check if remaining part is smaller than TAG
size, then reset TX_MAX to be TAG starting sequence number.

Fixes: 5a4b9fe7fe ("cxgb4/chcr: complete record tx handling")
Signed-off-by: Rohit Maheshwari <rohitm@chelsio.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-11 16:30:37 -08:00
..
ch_ipsec cxgb4/ch_ipsec: Replace the module name to ch_ipsec from chcr 2020-10-15 09:28:34 -07:00
ch_ktls ch_ktls: Correction in middle record handling 2020-11-11 16:30:37 -08:00
chtls chelsio/chtls: fix always leaking ctrl_skb 2020-11-03 13:50:15 -08:00
Kconfig net: chelsio: inline_crypto: fix Kconfig and build errors 2020-10-20 18:15:53 -07:00
Makefile crypto/chcr: move nic TLS functionality to drivers/net 2020-09-11 17:26:39 -07:00