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5d93cfcf73
This converts DPAA to phylink. All macs are converted. This should work with no device tree modifications (including those made in this series), except for QSGMII (as noted previously). The mEMAC configuration is one of the tricker areas. I have tried to capture all the restrictions across the various models. Most of the time, we assume that if the serdes supports a mode or the phy-interface-mode specifies it, then we support it. The only place we can't do this is (RG)MII, since there's no serdes. In that case, we rely on a (new) devicetree property. There are also several cases where half-duplex is broken. Unfortunately, only a single compatible is used for the MAC, so we have to use the board compatible instead. The 10GEC conversion is very straightforward, since it only supports XAUI. There is generally nothing to configure. The dTSEC conversion is broadly similar to mEMAC, but is simpler because we don't support configuring the SerDes (though this can be easily added) and we don't have multiple PCSs. From what I can tell, there's nothing different in the driver or documentation between SGMII and 1000BASE-X except for the advertising. Similarly, I couldn't find anything about 2500BASE-X. In both cases, I treat them like SGMII. These modes aren't used by any in-tree boards. Similarly, despite being mentioned in the driver, I couldn't find any documented SoCs which supported QSGMII. I have left it unimplemented for now. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: David S. Miller <davem@davemloft.net>
41 lines
1.6 KiB
Text
41 lines
1.6 KiB
Text
# SPDX-License-Identifier: GPL-2.0-only
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config FSL_FMAN
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tristate "FMan support"
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depends on FSL_SOC || ARCH_LAYERSCAPE || COMPILE_TEST
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select GENERIC_ALLOCATOR
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select PHYLINK
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select PCS
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select PCS_LYNX
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select CRC32
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default n
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help
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Freescale Data-Path Acceleration Architecture Frame Manager
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(FMan) support
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config DPAA_ERRATUM_A050385
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bool
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depends on ARM64 && FSL_DPAA
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default y
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help
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DPAA FMan erratum A050385 software workaround implementation:
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align buffers, data start, SG fragment length to avoid FMan DMA
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splits.
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FMAN DMA read or writes under heavy traffic load may cause FMAN
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internal resource leak thus stopping further packet processing.
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The FMAN internal queue can overflow when FMAN splits single
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read or write transactions into multiple smaller transactions
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such that more than 17 AXI transactions are in flight from FMAN
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to interconnect. When the FMAN internal queue overflows, it can
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stall further packet processing. The issue can occur with any
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one of the following three conditions:
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1. FMAN AXI transaction crosses 4K address boundary (Errata
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A010022)
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2. FMAN DMA address for an AXI transaction is not 16 byte
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aligned, i.e. the last 4 bits of an address are non-zero
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3. Scatter Gather (SG) frames have more than one SG buffer in
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the SG list and any one of the buffers, except the last
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buffer in the SG list has data size that is not a multiple
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of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
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With any one of the above three conditions present, there is
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likelihood of stalled FMAN packet processing, especially under
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stress with multiple ports injecting line-rate traffic.
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