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59dc5bfca0
When an interrupt is taken, the SRR registers are set to return to where it left off. Unless they are modified in the meantime, or the return address or MSR are modified, there is no need to reload these registers when returning from interrupt. Introduce per-CPU flags that track the validity of SRR and HSRR registers. These are cleared when returning from interrupt, when using the registers for something else (e.g., OPAL calls), when adjusting the return address or MSR of a context, and when context switching (which changes the return address and MSR). This improves the performance of interrupt returns. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [mpe: Fold in fixup patch from Nick] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20210617155116.2167984-5-npiggin@gmail.com
195 lines
4.9 KiB
C
195 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* mpc7448_hpc2.c
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*
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* Board setup routines for the Freescale mpc7448hpc2(taiga) platform
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*
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* Author: Jacob Pan
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* jacob.pan@freescale.com
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* Author: Xianghua Xiao
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* x.xiao@freescale.com
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* Maintainer: Roy Zang <tie-fei.zang@freescale.com>
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* Add Flat Device Tree support fot mpc7448hpc2 board
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*
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* Copyright 2004-2006 Freescale Semiconductor, Inc.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/console.h>
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#include <linux/extable.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#include <linux/serial.h>
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#include <linux/tty.h>
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#include <linux/serial_core.h>
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#include <asm/time.h>
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#include <asm/machdep.h>
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#include <asm/prom.h>
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#include <asm/udbg.h>
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#include <asm/tsi108.h>
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#include <asm/pci-bridge.h>
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#include <asm/reg.h>
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#include <mm/mmu_decl.h>
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#include <asm/tsi108_pci.h>
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#include <asm/tsi108_irq.h>
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#include <asm/mpic.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt...) do { printk(fmt); } while(0)
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#else
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#define DBG(fmt...) do { } while(0)
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#endif
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#define MPC7448HPC2_PCI_CFG_PHYS 0xfb000000
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int mpc7448_hpc2_exclude_device(struct pci_controller *hose,
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u_char bus, u_char devfn)
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{
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if (bus == 0 && PCI_SLOT(devfn) == 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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else
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return PCIBIOS_SUCCESSFUL;
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}
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static void __init mpc7448_hpc2_setup_pci(void)
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{
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#ifdef CONFIG_PCI
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struct device_node *np;
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if (ppc_md.progress)
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ppc_md.progress("mpc7448_hpc2_setup_pci():set_bridge", 0);
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/* setup PCI host bridge */
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for_each_compatible_node(np, "pci", "tsi108-pci")
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tsi108_setup_pci(np, MPC7448HPC2_PCI_CFG_PHYS, 0);
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ppc_md.pci_exclude_device = mpc7448_hpc2_exclude_device;
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if (ppc_md.progress)
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ppc_md.progress("tsi108: resources set", 0x100);
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#endif
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}
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static void __init mpc7448_hpc2_setup_arch(void)
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{
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tsi108_csr_vir_base = get_vir_csrbase();
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printk(KERN_INFO "MPC7448HPC2 (TAIGA) Platform\n");
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printk(KERN_INFO
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"Jointly ported by Freescale and Tundra Semiconductor\n");
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printk(KERN_INFO
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"Enabling L2 cache then enabling the HID0 prefetch engine.\n");
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}
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/*
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* Interrupt setup and service. Interrupts on the mpc7448_hpc2 come
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* from the four external INT pins, PCI interrupts are routed via
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* PCI interrupt control registers, it generates internal IRQ23
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*
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* Interrupt routing on the Taiga Board:
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* TSI108:PB_INT[0] -> CPU0:INT#
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* TSI108:PB_INT[1] -> CPU0:MCP#
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* TSI108:PB_INT[2] -> N/C
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* TSI108:PB_INT[3] -> N/C
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*/
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static void __init mpc7448_hpc2_init_IRQ(void)
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{
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struct mpic *mpic;
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#ifdef CONFIG_PCI
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unsigned int cascade_pci_irq;
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struct device_node *tsi_pci;
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struct device_node *cascade_node = NULL;
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#endif
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mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
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MPIC_SPV_EOI | MPIC_NO_PTHROU_DIS | MPIC_REGSET_TSI108,
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24, 0,
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"Tsi108_PIC");
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BUG_ON(mpic == NULL);
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mpic_assign_isu(mpic, 0, mpic->paddr + 0x100);
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mpic_init(mpic);
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#ifdef CONFIG_PCI
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tsi_pci = of_find_node_by_type(NULL, "pci");
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if (tsi_pci == NULL) {
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printk("%s: No tsi108 pci node found !\n", __func__);
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return;
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}
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cascade_node = of_find_node_by_type(NULL, "pic-router");
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if (cascade_node == NULL) {
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printk("%s: No tsi108 pci cascade node found !\n", __func__);
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return;
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}
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cascade_pci_irq = irq_of_parse_and_map(tsi_pci, 0);
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DBG("%s: tsi108 cascade_pci_irq = 0x%x\n", __func__,
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(u32) cascade_pci_irq);
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tsi108_pci_int_init(cascade_node);
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irq_set_handler_data(cascade_pci_irq, mpic);
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irq_set_chained_handler(cascade_pci_irq, tsi108_irq_cascade);
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#endif
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/* Configure MPIC outputs to CPU0 */
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tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0);
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}
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void mpc7448_hpc2_show_cpuinfo(struct seq_file *m)
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{
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seq_printf(m, "vendor\t\t: Freescale Semiconductor\n");
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}
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static void __noreturn mpc7448_hpc2_restart(char *cmd)
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{
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local_irq_disable();
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/* Set exception prefix high - to the firmware */
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mtmsr(mfmsr() | MSR_IP);
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isync();
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for (;;) ; /* Spin until reset happens */
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}
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init mpc7448_hpc2_probe(void)
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{
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if (!of_machine_is_compatible("mpc74xx"))
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return 0;
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return 1;
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}
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static int mpc7448_machine_check_exception(struct pt_regs *regs)
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{
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const struct exception_table_entry *entry;
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/* Are we prepared to handle this fault */
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if ((entry = search_exception_tables(regs->nip)) != NULL) {
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tsi108_clear_pci_cfg_error();
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regs_set_return_msr(regs, regs->msr | MSR_RI);
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regs_set_return_ip(regs, extable_fixup(entry));
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return 1;
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}
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return 0;
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}
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define_machine(mpc7448_hpc2){
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.name = "MPC7448 HPC2",
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.probe = mpc7448_hpc2_probe,
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.setup_arch = mpc7448_hpc2_setup_arch,
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.discover_phbs = mpc7448_hpc2_setup_pci,
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.init_IRQ = mpc7448_hpc2_init_IRQ,
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.show_cpuinfo = mpc7448_hpc2_show_cpuinfo,
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.get_irq = mpic_get_irq,
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.restart = mpc7448_hpc2_restart,
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.calibrate_decr = generic_calibrate_decr,
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.machine_check_exception= mpc7448_machine_check_exception,
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.progress = udbg_progress,
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};
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