Mohammed Shafi Shajakhan 5269c65900 ath10k: fix CCK h/w rates for QCA99X0 and newer chipsets ... CCK hardware table mapping from QCA99X0 onwards got revised. The CCK hardware rate values are in a proper order wrt. to rate and preamble as below ATH10K_HW_RATE_REV2_CCK_LP_1M = 1, ATH10K_HW_RATE_REV2_CCK_LP_2M = 2, ATH10K_HW_RATE_REV2_CCK_LP_5_5M = 3, ATH10K_HW_RATE_REV2_CCK_LP_11M = 4, ATH10K_HW_RATE_REV2_CCK_SP_2M = 5, ATH10K_HW_RATE_REV2_CCK_SP_5_5M = 6, ATH10K_HW_RATE_REV2_CCK_SP_11M = 7, This results in reporting of rx frames (with CCK rates) totally wrong for QCA99X0, QCA4019. Fix this by having separate CCK rate table for these chipsets with rev2 suffix and registering the correct rate mapping to mac80211 based on the new hw_param (introduced) 'cck_rate_map_rev2' which shall be true for any newchipsets from QCA99X0 onwards Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>		2016-06-14 14:56:04 +03:00
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admtek
ath	ath10k: fix CCK h/w rates for QCA99X0 and newer chipsets	2016-06-14 14:56:04 +03:00
atmel	atmel: potential underflow in atmel_set_freq()	2016-05-11 22:02:20 +03:00
broadcom	brcmfmac: Add 4356 sdio support	2016-05-11 21:55:12 +03:00
cisco	airo: prevent potential underflow in airo_set_freq()	2016-05-11 22:01:38 +03:00
intel	* work for RX multiqueue continues (Sara);	2016-05-11 20:54:07 +03:00
intersil
marvell	mwifiex: fixup error messages	2016-05-11 22:00:47 +03:00
mediatek
ralink
realtek	rtlwifi: pci: use dev_kfree_skb_irq instead of kfree_skb in rtl_pci_reset_trx_ring	2016-05-11 21:59:04 +03:00
rsi
st
ti	wlcore/wl12xx: Fix fw logger over sdio	2016-05-11 21:26:15 +03:00
zydas
Kconfig
mac80211_hwsim.c
mac80211_hwsim.h
Makefile
ray_cs.c
ray_cs.h
rayctl.h
rndis_wlan.c
wl3501.h
wl3501_cs.c