linux/drivers/gpu/drm/amd/include
Huang Rui 517cb957c4 drm/amd/pm: implement the processor clocks which read by metric
The core processor clocks will be stored in smu metric table, then we
add this runtime information into amdgpu_pm_info interface.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-13 23:52:51 -05:00
..
asic_reg drm/amdgpu: add osssys v4_2 ip headers (v2) 2020-12-23 15:05:20 -05:00
ivsrcid drm/amdgpu: add sdma2 and sdma3 irqsrc header files for sienna_cichlid (v2) 2020-06-03 13:52:03 -04:00
amd_acpi.h
amd_pcie.h
amd_pcie_helpers.h
amd_shared.h drm/amdgpu: Add GFX Fine Grain Clock Gating flag 2020-11-04 17:08:08 -05:00
arct_ip_offset.h drm/amd/include/arct_ip_offset: Mark top-level IP_BASE definition as __maybe_unused 2020-11-24 12:09:53 -05:00
atom-bits.h
atom-names.h
atom-types.h
atombios.h drm/amd/pm: correct VR shared rail info 2020-10-27 11:58:57 -04:00
atomfirmware.h drm/amdgpu: new macro for determining 2ND_USB20PORT support 2020-12-10 16:41:49 -05:00
atomfirmwareid.h
cgs_common.h drm/amdgpu: retire indirect mmio reg support from cgs 2020-04-09 10:43:18 -04:00
cik_structs.h
dimgrey_cavefish_ip_offset.h drm/amd/include/dimgrey_cavefish_ip_offset: Mark top-level IP_BASE as __maybe_unused 2020-11-24 12:09:53 -05:00
discovery.h
displayobject.h
dm_pp_interface.h
kgd_kfd_interface.h drm next for 5.10-rc1 2020-10-15 10:46:16 -07:00
kgd_pp_interface.h drm/amd/pm: implement the processor clocks which read by metric 2021-01-13 23:52:51 -05:00
navi10_enum.h
navi10_ip_offset.h drm/amd/include/navi10_ip_offset: Mark top-level IP_BASE as __maybe_unused 2020-11-24 12:09:53 -05:00
navi12_ip_offset.h drm/amd/include/navi12_ip_offset: Mark top-level IP_BASE as __maybe_unused 2020-11-24 12:09:53 -05:00
navi14_ip_offset.h drm/amd/include/navi14_ip_offset: Mark top-level IP_BASE as __maybe_unused 2020-11-24 12:09:53 -05:00
pptable.h
renoir_ip_offset.h
sienna_cichlid_ip_offset.h drm/amd/include/sienna_cichlid_ip_offset: Mark top-level IP_BASE as __maybe_unused 2020-11-24 12:09:53 -05:00
soc15_hw_ip.h
soc15_ih_clientid.h drm/amdgpu: correct SDMA3 IH clinet id for sienna_cichlid 2020-06-03 13:52:04 -04:00
v9_structs.h
v10_structs.h
vangogh_ip_offset.h drm/amd/include/vangogh_ip_offset: Mark top-level IP_BASE as __maybe_unused 2020-11-24 12:09:53 -05:00
vega10_enum.h
vega10_ip_offset.h drm/amd/include/vega10_ip_offset: Mark _BASE structs as __maybe_unused 2020-11-13 17:29:46 -05:00
vega20_ip_offset.h drm/amd/include/vega20_ip_offset: Mark top-level IP_BASE definition as __maybe_unused 2020-11-24 12:09:53 -05:00
vi_structs.h