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514820eb98
Non-SCI parts do not have the special port reg necessary for cases where the RX and SCI pins are muxed and need to be manually polled, so these like always fall back on the normal FIFO processing paths. SH7760 is in a class in and of itself with regards to mapping its SIM card interface via the SCI port class despite not having any of the RXD lines wired up and so implicitly behaving more like a SCIF in this regard. Out of the other CPUs, some support the port check via the same block while others do it through an external SuperI/O, so it's not even possible to perform the check relative to the ioremapped cookie offset, so the separate read semantics are preserved here, too. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
303 lines
7.2 KiB
C
303 lines
7.2 KiB
C
/*
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* SH3 Setup code for SH7706, SH7707, SH7708, SH7709
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*
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* Copyright (C) 2007 Magnus Damm
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* Copyright (C) 2009 Paul Mundt
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*
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* Based on setup-sh7709.c
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*
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* Copyright (C) 2006 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/platform_device.h>
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#include <linux/serial.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_timer.h>
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
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PINT07, PINT815,
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DMAC, SCIF0, SCIF2, SCI, ADC_ADI,
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LCDC, PCC0, PCC1,
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TMU0, TMU1, TMU2,
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RTC, WDT, REF,
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
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INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
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INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
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INTC_VECT(RTC, 0x4c0),
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INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500),
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INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540),
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INTC_VECT(WDT, 0x560),
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INTC_VECT(REF, 0x580),
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INTC_VECT(REF, 0x5a0),
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#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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/* IRQ0->5 are handled in setup-sh3.c */
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INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
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INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
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INTC_VECT(ADC_ADI, 0x980),
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INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),
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INTC_VECT(SCIF2, 0x940), INTC_VECT(SCIF2, 0x960),
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
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INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
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INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7707)
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INTC_VECT(LCDC, 0x9a0),
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INTC_VECT(PCC0, 0x9c0), INTC_VECT(PCC1, 0x9e0),
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#endif
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};
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static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
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{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
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#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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{ 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
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{ 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
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{ 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } },
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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{ 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, } },
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{ 0xa400001a, 0, 16, 4, /* IPRE */ { 0, SCIF0 } },
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7707)
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{ 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },
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#endif
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};
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static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, NULL,
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NULL, prio_registers, NULL);
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static struct resource rtc_resources[] = {
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[0] = {
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.start = 0xfffffec0,
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.end = 0xfffffec0 + 0x1e,
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.flags = IORESOURCE_IO,
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},
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[1] = {
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.start = 20,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device rtc_device = {
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.name = "sh-rtc",
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.id = -1,
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.num_resources = ARRAY_SIZE(rtc_resources),
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.resource = rtc_resources,
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};
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static struct plat_sci_port scif0_platform_data = {
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.mapbase = 0xfffffe80,
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.port_reg = 0xa4000136,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_TE | SCSCR_RE,
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.scbrr_algo_id = SCBRR_ALGO_2,
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.type = PORT_SCI,
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.irqs = { 23, 23, 23, 0 },
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};
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static struct platform_device scif0_device = {
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.name = "sh-sci",
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.id = 0,
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.dev = {
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.platform_data = &scif0_platform_data,
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},
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};
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#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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static struct plat_sci_port scif1_platform_data = {
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.mapbase = 0xa4000150,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_TE | SCSCR_RE,
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.scbrr_algo_id = SCBRR_ALGO_2,
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.type = PORT_SCIF,
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.irqs = { 56, 56, 56, 56 },
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};
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static struct platform_device scif1_device = {
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.name = "sh-sci",
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.id = 1,
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.dev = {
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.platform_data = &scif1_platform_data,
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},
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};
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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static struct plat_sci_port scif2_platform_data = {
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.mapbase = 0xa4000140,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_TE | SCSCR_RE,
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.scbrr_algo_id = SCBRR_ALGO_2,
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.type = PORT_IRDA,
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.irqs = { 52, 52, 52, 52 },
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};
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static struct platform_device scif2_device = {
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.name = "sh-sci",
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.id = 2,
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.dev = {
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.platform_data = &scif2_platform_data,
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},
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};
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#endif
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static struct sh_timer_config tmu0_platform_data = {
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.channel_offset = 0x02,
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.timer_bit = 0,
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.clockevent_rating = 200,
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};
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static struct resource tmu0_resources[] = {
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[0] = {
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.start = 0xfffffe94,
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.end = 0xfffffe9f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 16,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu0_device = {
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.name = "sh_tmu",
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.id = 0,
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.dev = {
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.platform_data = &tmu0_platform_data,
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},
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.resource = tmu0_resources,
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.num_resources = ARRAY_SIZE(tmu0_resources),
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};
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static struct sh_timer_config tmu1_platform_data = {
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.channel_offset = 0xe,
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.timer_bit = 1,
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.clocksource_rating = 200,
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};
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static struct resource tmu1_resources[] = {
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[0] = {
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.start = 0xfffffea0,
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.end = 0xfffffeab,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 17,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu1_device = {
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.name = "sh_tmu",
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.id = 1,
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.dev = {
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.platform_data = &tmu1_platform_data,
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},
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.resource = tmu1_resources,
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.num_resources = ARRAY_SIZE(tmu1_resources),
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};
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static struct sh_timer_config tmu2_platform_data = {
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.channel_offset = 0x1a,
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.timer_bit = 2,
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};
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static struct resource tmu2_resources[] = {
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[0] = {
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.start = 0xfffffeac,
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.end = 0xfffffebb,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 18,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu2_device = {
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.name = "sh_tmu",
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.id = 2,
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.dev = {
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.platform_data = &tmu2_platform_data,
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},
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.resource = tmu2_resources,
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.num_resources = ARRAY_SIZE(tmu2_resources),
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};
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static struct platform_device *sh770x_devices[] __initdata = {
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&scif0_device,
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#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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&scif1_device,
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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&scif2_device,
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#endif
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&tmu0_device,
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&tmu1_device,
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&tmu2_device,
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&rtc_device,
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};
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static int __init sh770x_devices_setup(void)
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{
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return platform_add_devices(sh770x_devices,
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ARRAY_SIZE(sh770x_devices));
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}
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arch_initcall(sh770x_devices_setup);
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static struct platform_device *sh770x_early_devices[] __initdata = {
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&scif0_device,
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#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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&scif1_device,
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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&scif2_device,
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#endif
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&tmu0_device,
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&tmu1_device,
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&tmu2_device,
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};
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void __init plat_early_device_setup(void)
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{
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early_platform_add_devices(sh770x_early_devices,
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ARRAY_SIZE(sh770x_early_devices));
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}
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void __init plat_irq_setup(void)
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{
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register_intc_controller(&intc_desc);
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#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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plat_irq_setup_sh3();
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#endif
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}
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