Guo Ren 4e562c1166 csky: Improve tlb operation with help of asid ... There are two generations of tlb operation instruction for C-SKY. First generation is use mcr register and it need software do more things, second generation is use specific instructions, eg: tlbi.va, tlbi.vas, tlbi.alls We implemented the following functions: - flush_tlb_range (a range of entries) - flush_tlb_page (one entry) Above functions use asid from vma->mm to invalid tlb entries and we could use tlbi.vas instruction for newest generation csky cpu. - flush_tlb_kernel_range - flush_tlb_one Above functions don't care asid and it invalid the tlb entries only with vpn and we could use tlbi.vaas instruction for newest generat- ion csky cpu. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Arnd Bergmann <arnd@arndb.de>		2019-07-19 14:21:36 +08:00
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asid.c	csky: Add new asid lib code from arm	2019-07-19 14:21:36 +08:00
cachev1.c	csky: Cache and TLB routines	2018-10-25 23:36:19 +08:00
cachev2.c	csky: Cache and TLB routines	2018-10-25 23:36:19 +08:00
context.c	csky: Use generic asid algorithm to implement switch_mm	2019-07-19 14:21:36 +08:00
dma-mapping.c	csky: use the generic remapping dma alloc implementation	2018-12-01 18:07:16 +01:00
fault.c	csky: Fixup compile warning	2019-04-22 14:46:23 +08:00
highmem.c	treewide: add checks for the return value of memblock_alloc*()	2019-03-12 10:04:02 -07:00
init.c	csky: Revert mmu ASID mechanism	2019-07-19 14:21:36 +08:00
ioremap.c	csky: Fixup io-range page attribute for mmap("/dev/mem")	2019-02-13 09:48:14 +08:00
Makefile	csky: Use generic asid algorithm to implement switch_mm	2019-07-19 14:21:36 +08:00
syscache.c	csky: Cache and TLB routines	2018-10-25 23:36:19 +08:00
tlb.c	csky: Improve tlb operation with help of asid	2019-07-19 14:21:36 +08:00