linux/drivers/infiniband/hw/mlx5
Jason Gunthorpe 49b99314b4 IB/mlx5: Flow through a more detailed return code from get_prefetchable_mr()
The error returns for various cases detected by get_prefetchable_mr() get
confused as it flows back to userspace. Properly label each error path and
flow the error code properly back to the system call.

Link: https://lore.kernel.org/r/20210928170846.GA1721590@nvidia.com
Suggested-by: Li Zhijian <lizhijian@cn.fujitsu.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2021-10-01 11:40:07 -03:00
..
ah.c
cmd.c IB/mlx5: Enable UAR to have DevX UID 2021-09-28 18:31:21 +03:00
cmd.h IB/mlx5: Enable UAR to have DevX UID 2021-09-28 18:31:21 +03:00
cong.c
counters.c RDMA: Split the alloc_hw_stats() ops to port and device variants 2021-06-16 20:58:29 -03:00
counters.h
cq.c Merge branch 'sg_nents' into rdma.git for-next 2021-08-30 09:49:59 -03:00
devx.c Merge branch 'sg_nents' into rdma.git for-next 2021-08-30 09:49:59 -03:00
devx.h
dm.c
dm.h
doorbell.c RDMA: Use the sg_table directly and remove the opencoded version from umem 2021-08-24 19:52:40 -03:00
fs.c Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net 2021-06-18 19:47:02 -07:00
fs.h
gsi.c RDMA: Globally allocate and release QP memory 2021-08-03 13:44:27 -03:00
ib_rep.c RDMA/mlx5: Add shared FDB support 2021-08-05 13:49:24 -07:00
ib_rep.h
ib_virt.c
Kconfig
mad.c
main.c IB/mlx5: Enable UAR to have DevX UID 2021-09-28 18:31:21 +03:00
Makefile
mem.c
mlx5_ib.h RDMA: Globally allocate and release QP memory 2021-08-03 13:44:27 -03:00
mr.c RDMA/mlx5: Fix xlt_chunk_align calculation 2021-09-08 08:31:10 -03:00
odp.c IB/mlx5: Flow through a more detailed return code from get_prefetchable_mr() 2021-10-01 11:40:07 -03:00
qos.c
qp.c RDMA/mlx5: Relax DCS QP creation checks 2021-08-30 09:47:40 -03:00
qp.h
qpc.c
restrack.c
restrack.h
srq.c
srq.h
srq_cmd.c
std_types.c RDMA/mlx5: Fill port info based on the relevant eswitch 2021-08-05 13:49:24 -07:00
wr.c RDMA/mlx5: Enable Relaxed Ordering by default for kernel ULPs 2021-06-21 12:33:08 -03:00
wr.h