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481f576c6c
[Why] The DISPCLK value was previously requested to be 15% higher for all ASICs that went through the dce110 bandwidth code path. As part of a refactoring of dce_clocks and the dce110 set bandwidth codepath this was removed for power saving considerations. That change caused display corruption under certain hardware configurations with Vega10. [How] The 15% DISPCLK increase is brought back but only on dce110 for now. This is should be a temporary workaround until the root cause is sorted out for why this occurs on Vega (or other ASICs, if reported). Tested-by: Nick Sarnie <sarnex@gentoo.org> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
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| .. | ||
| dce_abm.c | ||
| dce_abm.h | ||
| dce_audio.c | ||
| dce_audio.h | ||
| dce_aux.c | ||
| dce_aux.h | ||
| dce_clock_source.c | ||
| dce_clock_source.h | ||
| dce_clocks.c | ||
| dce_clocks.h | ||
| dce_dmcu.c | ||
| dce_dmcu.h | ||
| dce_hwseq.c | ||
| dce_hwseq.h | ||
| dce_i2c.c | ||
| dce_i2c.h | ||
| dce_i2c_hw.c | ||
| dce_i2c_hw.h | ||
| dce_i2c_sw.c | ||
| dce_i2c_sw.h | ||
| dce_ipp.c | ||
| dce_ipp.h | ||
| dce_link_encoder.c | ||
| dce_link_encoder.h | ||
| dce_mem_input.c | ||
| dce_mem_input.h | ||
| dce_opp.c | ||
| dce_opp.h | ||
| dce_scl_filters.c | ||
| dce_stream_encoder.c | ||
| dce_stream_encoder.h | ||
| dce_transform.c | ||
| dce_transform.h | ||
| Makefile | ||