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9f786d033d
Tell the PCI core about host bridge address translation so it can take care of bus-to-resource conversion for us. CC: Russell King <linux@arm.linux.org.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
614 lines
17 KiB
C
614 lines
17 KiB
C
/*
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* linux/arch/arm/mach-integrator/pci_v3.c
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*
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* PCI functions for V3 host PCI bridge
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*
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* Copyright (C) 1999 ARM Limited
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* Copyright (C) 2000-2001 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#include <asm/irq.h>
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#include <asm/signal.h>
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#include <asm/system.h>
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#include <asm/mach/pci.h>
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#include <asm/irq_regs.h>
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#include <asm/hardware/pci_v3.h>
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/*
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* The V3 PCI interface chip in Integrator provides several windows from
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* local bus memory into the PCI memory areas. Unfortunately, there
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* are not really enough windows for our usage, therefore we reuse
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* one of the windows for access to PCI configuration space. The
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* memory map is as follows:
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*
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* Local Bus Memory Usage
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*
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* 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable
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* 50000000 - 5FFFFFFF PCI memory. 256M prefetchable
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* 60000000 - 60FFFFFF PCI IO. 16M
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* 61000000 - 61FFFFFF PCI Configuration. 16M
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*
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* There are three V3 windows, each described by a pair of V3 registers.
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* These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2.
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* Base0 and Base1 can be used for any type of PCI memory access. Base2
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* can be used either for PCI I/O or for I20 accesses. By default, uHAL
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* uses this only for PCI IO space.
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*
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* Normally these spaces are mapped using the following base registers:
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*
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* Usage Local Bus Memory Base/Map registers used
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*
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* Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
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* Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1
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* IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
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* Cfg 61000000 - 61FFFFFF
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*
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* This means that I20 and PCI configuration space accesses will fail.
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* When PCI configuration accesses are needed (via the uHAL PCI
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* configuration space primitives) we must remap the spaces as follows:
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*
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* Usage Local Bus Memory Base/Map registers used
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*
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* Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
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* Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0
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* IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
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* Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1
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*
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* To make this work, the code depends on overlapping windows working.
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* The V3 chip translates an address by checking its range within
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* each of the BASE/MAP pairs in turn (in ascending register number
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* order). It will use the first matching pair. So, for example,
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* if the same address is mapped by both LB_BASE0/LB_MAP0 and
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* LB_BASE1/LB_MAP1, the V3 will use the translation from
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* LB_BASE0/LB_MAP0.
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*
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* To allow PCI Configuration space access, the code enlarges the
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* window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes
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* the windows currently mapped by LB_BASE1/LB_MAP1 so that it can
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* be remapped for use by configuration cycles.
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*
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* At the end of the PCI Configuration space accesses,
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* LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window
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* mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to
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* reveal the now restored LB_BASE1/LB_MAP1 window.
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*
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* NOTE: We do not set up I2O mapping. I suspect that this is only
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* for an intelligent (target) device. Using I2O disables most of
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* the mappings into PCI memory.
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*/
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// V3 access routines
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#define v3_writeb(o,v) __raw_writeb(v, PCI_V3_VADDR + (unsigned int)(o))
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#define v3_readb(o) (__raw_readb(PCI_V3_VADDR + (unsigned int)(o)))
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#define v3_writew(o,v) __raw_writew(v, PCI_V3_VADDR + (unsigned int)(o))
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#define v3_readw(o) (__raw_readw(PCI_V3_VADDR + (unsigned int)(o)))
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#define v3_writel(o,v) __raw_writel(v, PCI_V3_VADDR + (unsigned int)(o))
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#define v3_readl(o) (__raw_readl(PCI_V3_VADDR + (unsigned int)(o)))
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/*============================================================================
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*
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* routine: uHALir_PCIMakeConfigAddress()
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*
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* parameters: bus = which bus
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* device = which device
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* function = which function
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* offset = configuration space register we are interested in
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*
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* description: this routine will generate a platform dependent config
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* address.
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*
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* calls: none
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*
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* returns: configuration address to play on the PCI bus
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*
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* To generate the appropriate PCI configuration cycles in the PCI
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* configuration address space, you present the V3 with the following pattern
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* (which is very nearly a type 1 (except that the lower two bits are 00 and
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* not 01). In order for this mapping to work you need to set up one of
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* the local to PCI aperatures to 16Mbytes in length translating to
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* PCI configuration space starting at 0x0000.0000.
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*
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* PCI configuration cycles look like this:
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*
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* Type 0:
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*
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* 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
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* 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*
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* 31:11 Device select bit.
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* 10:8 Function number
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* 7:2 Register number
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*
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* Type 1:
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*
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* 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
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* 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*
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* 31:24 reserved
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* 23:16 bus number (8 bits = 128 possible buses)
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* 15:11 Device number (5 bits)
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* 10:8 function number
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* 7:2 register number
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*
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*/
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static DEFINE_RAW_SPINLOCK(v3_lock);
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#define PCI_BUS_NONMEM_START 0x00000000
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#define PCI_BUS_NONMEM_SIZE SZ_256M
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#define PCI_BUS_PREMEM_START PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE
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#define PCI_BUS_PREMEM_SIZE SZ_256M
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#if PCI_BUS_NONMEM_START & 0x000fffff
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#error PCI_BUS_NONMEM_START must be megabyte aligned
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#endif
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#if PCI_BUS_PREMEM_START & 0x000fffff
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#error PCI_BUS_PREMEM_START must be megabyte aligned
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#endif
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#undef V3_LB_BASE_PREFETCH
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#define V3_LB_BASE_PREFETCH 0
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static unsigned long v3_open_config_window(struct pci_bus *bus,
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unsigned int devfn, int offset)
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{
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unsigned int address, mapaddress, busnr;
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busnr = bus->number;
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/*
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* Trap out illegal values
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*/
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if (offset > 255)
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BUG();
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if (busnr > 255)
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BUG();
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if (devfn > 255)
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BUG();
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if (busnr == 0) {
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int slot = PCI_SLOT(devfn);
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/*
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* local bus segment so need a type 0 config cycle
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*
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* build the PCI configuration "address" with one-hot in
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* A31-A11
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*
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* mapaddress:
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* 3:1 = config cycle (101)
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* 0 = PCI A1 & A0 are 0 (0)
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*/
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address = PCI_FUNC(devfn) << 8;
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mapaddress = V3_LB_MAP_TYPE_CONFIG;
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if (slot > 12)
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/*
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* high order bits are handled by the MAP register
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*/
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mapaddress |= 1 << (slot - 5);
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else
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/*
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* low order bits handled directly in the address
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*/
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address |= 1 << (slot + 11);
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} else {
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/*
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* not the local bus segment so need a type 1 config cycle
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*
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* address:
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* 23:16 = bus number
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* 15:11 = slot number (7:3 of devfn)
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* 10:8 = func number (2:0 of devfn)
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*
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* mapaddress:
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* 3:1 = config cycle (101)
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* 0 = PCI A1 & A0 from host bus (1)
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*/
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mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
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address = (busnr << 16) | (devfn << 8);
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}
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/*
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* Set up base0 to see all 512Mbytes of memory space (not
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* prefetchable), this frees up base1 for re-use by
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* configuration memory
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*/
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v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
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V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
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/*
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* Set up base1/map1 to point into configuration space.
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*/
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v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) |
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V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
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v3_writew(V3_LB_MAP1, mapaddress);
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return PCI_CONFIG_VADDR + address + offset;
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}
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static void v3_close_config_window(void)
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{
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/*
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* Reassign base1 for use by prefetchable PCI memory
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*/
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v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
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V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
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V3_LB_BASE_ENABLE);
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v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
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V3_LB_MAP_TYPE_MEM_MULTIPLE);
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/*
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* And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
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*/
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v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
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V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
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}
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static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 *val)
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{
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unsigned long addr;
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unsigned long flags;
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u32 v;
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raw_spin_lock_irqsave(&v3_lock, flags);
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addr = v3_open_config_window(bus, devfn, where);
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switch (size) {
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case 1:
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v = __raw_readb(addr);
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break;
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case 2:
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v = __raw_readw(addr);
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break;
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default:
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v = __raw_readl(addr);
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break;
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}
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v3_close_config_window();
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raw_spin_unlock_irqrestore(&v3_lock, flags);
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*val = v;
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return PCIBIOS_SUCCESSFUL;
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}
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static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 val)
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{
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unsigned long addr;
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unsigned long flags;
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raw_spin_lock_irqsave(&v3_lock, flags);
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addr = v3_open_config_window(bus, devfn, where);
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switch (size) {
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case 1:
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__raw_writeb((u8)val, addr);
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__raw_readb(addr);
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break;
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case 2:
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__raw_writew((u16)val, addr);
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__raw_readw(addr);
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break;
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case 4:
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__raw_writel(val, addr);
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__raw_readl(addr);
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break;
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}
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v3_close_config_window();
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raw_spin_unlock_irqrestore(&v3_lock, flags);
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops pci_v3_ops = {
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.read = v3_read_config,
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.write = v3_write_config,
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};
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static struct resource non_mem = {
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.name = "PCI non-prefetchable",
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.start = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START,
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.end = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct resource pre_mem = {
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.name = "PCI prefetchable",
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.start = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START,
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.end = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START + PCI_BUS_PREMEM_SIZE - 1,
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.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
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};
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static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
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{
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if (request_resource(&iomem_resource, &non_mem)) {
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printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
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"memory region\n");
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return -EBUSY;
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}
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if (request_resource(&iomem_resource, &pre_mem)) {
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release_resource(&non_mem);
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printk(KERN_ERR "PCI: unable to allocate prefetchable "
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"memory region\n");
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return -EBUSY;
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}
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/*
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* the IO resource for this bus
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* the mem resource for this bus
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* the prefetch mem resource for this bus
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*/
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pci_add_resource_offset(&sys->resources,
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&ioport_resource, sys->io_offset);
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pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
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pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);
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return 1;
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}
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/*
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* These don't seem to be implemented on the Integrator I have, which
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* means I can't get additional information on the reason for the pm2fb
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* problems. I suppose I'll just have to mind-meld with the machine. ;)
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*/
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#define SC_PCI IO_ADDRESS(INTEGRATOR_SC_PCIENABLE)
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#define SC_LBFADDR IO_ADDRESS(INTEGRATOR_SC_BASE + 0x20)
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#define SC_LBFCODE IO_ADDRESS(INTEGRATOR_SC_BASE + 0x24)
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static int
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v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
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{
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unsigned long pc = instruction_pointer(regs);
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unsigned long instr = *(unsigned long *)pc;
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#if 0
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char buf[128];
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sprintf(buf, "V3 fault: addr 0x%08lx, FSR 0x%03x, PC 0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n",
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addr, fsr, pc, instr, __raw_readl(SC_LBFADDR), __raw_readl(SC_LBFCODE) & 255,
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v3_readb(V3_LB_ISTAT));
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printk(KERN_DEBUG "%s", buf);
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#endif
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v3_writeb(V3_LB_ISTAT, 0);
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__raw_writel(3, SC_PCI);
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/*
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* If the instruction being executed was a read,
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* make it look like it read all-ones.
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*/
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if ((instr & 0x0c100000) == 0x04100000) {
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int reg = (instr >> 12) & 15;
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unsigned long val;
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if (instr & 0x00400000)
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val = 255;
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else
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val = -1;
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regs->uregs[reg] = val;
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regs->ARM_pc += 4;
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return 0;
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}
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if ((instr & 0x0e100090) == 0x00100090) {
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int reg = (instr >> 12) & 15;
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regs->uregs[reg] = -1;
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regs->ARM_pc += 4;
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return 0;
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}
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return 1;
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}
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static irqreturn_t v3_irq(int dummy, void *devid)
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{
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#ifdef CONFIG_DEBUG_LL
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struct pt_regs *regs = get_irq_regs();
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unsigned long pc = instruction_pointer(regs);
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unsigned long instr = *(unsigned long *)pc;
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char buf[128];
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extern void printascii(const char *);
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sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x "
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"ISTAT=%02x\n", IRQ_AP_V3INT, pc, instr,
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__raw_readl(SC_LBFADDR),
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__raw_readl(SC_LBFCODE) & 255,
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v3_readb(V3_LB_ISTAT));
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printascii(buf);
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#endif
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v3_writew(V3_PCI_STAT, 0xf000);
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v3_writeb(V3_LB_ISTAT, 0);
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__raw_writel(3, SC_PCI);
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#ifdef CONFIG_DEBUG_LL
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/*
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* If the instruction being executed was a read,
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* make it look like it read all-ones.
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*/
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if ((instr & 0x0c100000) == 0x04100000) {
|
|
int reg = (instr >> 16) & 15;
|
|
sprintf(buf, " reg%d = %08lx\n", reg, regs->uregs[reg]);
|
|
printascii(buf);
|
|
}
|
|
#endif
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
|
|
{
|
|
int ret = 0;
|
|
|
|
if (nr == 0) {
|
|
sys->mem_offset = PHYS_PCI_MEM_BASE;
|
|
ret = pci_v3_setup_resources(sys);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
struct pci_bus * __init pci_v3_scan_bus(int nr, struct pci_sys_data *sys)
|
|
{
|
|
return pci_scan_root_bus(NULL, sys->busnr, &pci_v3_ops, sys,
|
|
&sys->resources);
|
|
}
|
|
|
|
/*
|
|
* V3_LB_BASE? - local bus address
|
|
* V3_LB_MAP? - pci bus address
|
|
*/
|
|
void __init pci_v3_preinit(void)
|
|
{
|
|
unsigned long flags;
|
|
unsigned int temp;
|
|
int ret;
|
|
|
|
pcibios_min_io = 0x6000;
|
|
pcibios_min_mem = 0x00100000;
|
|
|
|
/*
|
|
* Hook in our fault handler for PCI errors
|
|
*/
|
|
hook_fault_code(4, v3_pci_fault, SIGBUS, 0, "external abort on linefetch");
|
|
hook_fault_code(6, v3_pci_fault, SIGBUS, 0, "external abort on linefetch");
|
|
hook_fault_code(8, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
|
|
hook_fault_code(10, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
|
|
|
|
raw_spin_lock_irqsave(&v3_lock, flags);
|
|
|
|
/*
|
|
* Unlock V3 registers, but only if they were previously locked.
|
|
*/
|
|
if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK)
|
|
v3_writew(V3_SYSTEM, 0xa05f);
|
|
|
|
/*
|
|
* Setup window 0 - PCI non-prefetchable memory
|
|
* Local: 0x40000000 Bus: 0x00000000 Size: 256MB
|
|
*/
|
|
v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
|
|
V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
|
|
v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(PCI_BUS_NONMEM_START) |
|
|
V3_LB_MAP_TYPE_MEM);
|
|
|
|
/*
|
|
* Setup window 1 - PCI prefetchable memory
|
|
* Local: 0x50000000 Bus: 0x10000000 Size: 256MB
|
|
*/
|
|
v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
|
|
V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
|
|
V3_LB_BASE_ENABLE);
|
|
v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
|
|
V3_LB_MAP_TYPE_MEM_MULTIPLE);
|
|
|
|
/*
|
|
* Setup window 2 - PCI IO
|
|
*/
|
|
v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(PHYS_PCI_IO_BASE) |
|
|
V3_LB_BASE_ENABLE);
|
|
v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0));
|
|
|
|
/*
|
|
* Disable PCI to host IO cycles
|
|
*/
|
|
temp = v3_readw(V3_PCI_CFG) & ~V3_PCI_CFG_M_I2O_EN;
|
|
temp |= V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS;
|
|
v3_writew(V3_PCI_CFG, temp);
|
|
|
|
printk(KERN_DEBUG "FIFO_CFG: %04x FIFO_PRIO: %04x\n",
|
|
v3_readw(V3_FIFO_CFG), v3_readw(V3_FIFO_PRIORITY));
|
|
|
|
/*
|
|
* Set the V3 FIFO such that writes have higher priority than
|
|
* reads, and local bus write causes local bus read fifo flush.
|
|
* Same for PCI.
|
|
*/
|
|
v3_writew(V3_FIFO_PRIORITY, 0x0a0a);
|
|
|
|
/*
|
|
* Re-lock the system register.
|
|
*/
|
|
temp = v3_readw(V3_SYSTEM) | V3_SYSTEM_M_LOCK;
|
|
v3_writew(V3_SYSTEM, temp);
|
|
|
|
/*
|
|
* Clear any error conditions, and enable write errors.
|
|
*/
|
|
v3_writeb(V3_LB_ISTAT, 0);
|
|
v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10));
|
|
v3_writeb(V3_LB_IMASK, 0x28);
|
|
__raw_writel(3, SC_PCI);
|
|
|
|
/*
|
|
* Grab the PCI error interrupt.
|
|
*/
|
|
ret = request_irq(IRQ_AP_V3INT, v3_irq, 0, "V3", NULL);
|
|
if (ret)
|
|
printk(KERN_ERR "PCI: unable to grab PCI error "
|
|
"interrupt: %d\n", ret);
|
|
|
|
raw_spin_unlock_irqrestore(&v3_lock, flags);
|
|
}
|
|
|
|
void __init pci_v3_postinit(void)
|
|
{
|
|
unsigned int pci_cmd;
|
|
|
|
pci_cmd = PCI_COMMAND_MEMORY |
|
|
PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
|
|
|
|
v3_writew(V3_PCI_CMD, pci_cmd);
|
|
|
|
v3_writeb(V3_LB_ISTAT, ~0x40);
|
|
v3_writeb(V3_LB_IMASK, 0x68);
|
|
|
|
#if 0
|
|
ret = request_irq(IRQ_AP_LBUSTIMEOUT, lb_timeout, 0, "bus timeout", NULL);
|
|
if (ret)
|
|
printk(KERN_ERR "PCI: unable to grab local bus timeout "
|
|
"interrupt: %d\n", ret);
|
|
#endif
|
|
|
|
register_isa_ports(PHYS_PCI_MEM_BASE, PHYS_PCI_IO_BASE, 0);
|
|
}
|