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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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472fcea160
The same logic to disable/enable port, set eee and get ethtool stats is used by drivers based on qca8k family switch. Move it to common code to make it accessible also by other drivers. While at it also drop unnecessary qca8k_priv cast for void pointers. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
277 lines
7 KiB
C
277 lines
7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
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* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2016 John Crispin <john@phrozen.org>
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*/
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#include <linux/netdevice.h>
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#include <net/dsa.h>
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#include "qca8k.h"
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#define MIB_DESC(_s, _o, _n) \
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{ \
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.size = (_s), \
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.offset = (_o), \
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.name = (_n), \
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}
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const struct qca8k_mib_desc ar8327_mib[] = {
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MIB_DESC(1, 0x00, "RxBroad"),
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MIB_DESC(1, 0x04, "RxPause"),
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MIB_DESC(1, 0x08, "RxMulti"),
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MIB_DESC(1, 0x0c, "RxFcsErr"),
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MIB_DESC(1, 0x10, "RxAlignErr"),
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MIB_DESC(1, 0x14, "RxRunt"),
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MIB_DESC(1, 0x18, "RxFragment"),
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MIB_DESC(1, 0x1c, "Rx64Byte"),
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MIB_DESC(1, 0x20, "Rx128Byte"),
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MIB_DESC(1, 0x24, "Rx256Byte"),
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MIB_DESC(1, 0x28, "Rx512Byte"),
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MIB_DESC(1, 0x2c, "Rx1024Byte"),
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MIB_DESC(1, 0x30, "Rx1518Byte"),
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MIB_DESC(1, 0x34, "RxMaxByte"),
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MIB_DESC(1, 0x38, "RxTooLong"),
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MIB_DESC(2, 0x3c, "RxGoodByte"),
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MIB_DESC(2, 0x44, "RxBadByte"),
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MIB_DESC(1, 0x4c, "RxOverFlow"),
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MIB_DESC(1, 0x50, "Filtered"),
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MIB_DESC(1, 0x54, "TxBroad"),
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MIB_DESC(1, 0x58, "TxPause"),
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MIB_DESC(1, 0x5c, "TxMulti"),
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MIB_DESC(1, 0x60, "TxUnderRun"),
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MIB_DESC(1, 0x64, "Tx64Byte"),
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MIB_DESC(1, 0x68, "Tx128Byte"),
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MIB_DESC(1, 0x6c, "Tx256Byte"),
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MIB_DESC(1, 0x70, "Tx512Byte"),
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MIB_DESC(1, 0x74, "Tx1024Byte"),
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MIB_DESC(1, 0x78, "Tx1518Byte"),
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MIB_DESC(1, 0x7c, "TxMaxByte"),
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MIB_DESC(1, 0x80, "TxOverSize"),
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MIB_DESC(2, 0x84, "TxByte"),
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MIB_DESC(1, 0x8c, "TxCollision"),
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MIB_DESC(1, 0x90, "TxAbortCol"),
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MIB_DESC(1, 0x94, "TxMultiCol"),
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MIB_DESC(1, 0x98, "TxSingleCol"),
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MIB_DESC(1, 0x9c, "TxExcDefer"),
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MIB_DESC(1, 0xa0, "TxDefer"),
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MIB_DESC(1, 0xa4, "TxLateCol"),
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MIB_DESC(1, 0xa8, "RXUnicast"),
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MIB_DESC(1, 0xac, "TXUnicast"),
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};
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int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
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{
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return regmap_read(priv->regmap, reg, val);
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}
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int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
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{
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return regmap_write(priv->regmap, reg, val);
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}
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int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
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{
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return regmap_update_bits(priv->regmap, reg, mask, write_val);
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}
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static const struct regmap_range qca8k_readable_ranges[] = {
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regmap_reg_range(0x0000, 0x00e4), /* Global control */
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regmap_reg_range(0x0100, 0x0168), /* EEE control */
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regmap_reg_range(0x0200, 0x0270), /* Parser control */
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regmap_reg_range(0x0400, 0x0454), /* ACL */
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regmap_reg_range(0x0600, 0x0718), /* Lookup */
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regmap_reg_range(0x0800, 0x0b70), /* QM */
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regmap_reg_range(0x0c00, 0x0c80), /* PKT */
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regmap_reg_range(0x0e00, 0x0e98), /* L3 */
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regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
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regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
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regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
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regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
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regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
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regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
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regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
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};
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const struct regmap_access_table qca8k_readable_table = {
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.yes_ranges = qca8k_readable_ranges,
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.n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
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};
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/* TODO: remove these extra ops when we can support regmap bulk read/write */
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int qca8k_bulk_read(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
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{
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int i, count = len / sizeof(u32), ret;
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if (priv->mgmt_master && priv->info->ops->read_eth &&
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!priv->info->ops->read_eth(priv, reg, val, len))
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return 0;
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for (i = 0; i < count; i++) {
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ret = regmap_read(priv->regmap, reg + (i * 4), val + i);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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/* TODO: remove these extra ops when we can support regmap bulk read/write */
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int qca8k_bulk_write(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
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{
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int i, count = len / sizeof(u32), ret;
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u32 tmp;
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if (priv->mgmt_master && priv->info->ops->write_eth &&
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!priv->info->ops->write_eth(priv, reg, val, len))
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return 0;
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for (i = 0; i < count; i++) {
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tmp = val[i];
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ret = regmap_write(priv->regmap, reg + (i * 4), tmp);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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int qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
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{
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u32 val;
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return regmap_read_poll_timeout(priv->regmap, reg, val, !(val & mask), 0,
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QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC);
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}
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int qca8k_mib_init(struct qca8k_priv *priv)
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{
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int ret;
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mutex_lock(&priv->reg_mutex);
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ret = regmap_update_bits(priv->regmap, QCA8K_REG_MIB,
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QCA8K_MIB_FUNC | QCA8K_MIB_BUSY,
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FIELD_PREP(QCA8K_MIB_FUNC, QCA8K_MIB_FLUSH) |
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QCA8K_MIB_BUSY);
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if (ret)
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goto exit;
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ret = qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
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if (ret)
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goto exit;
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ret = regmap_set_bits(priv->regmap, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
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if (ret)
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goto exit;
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ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
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exit:
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mutex_unlock(&priv->reg_mutex);
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return ret;
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}
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void qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
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{
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u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
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/* Port 0 and 6 have no internal PHY */
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if (port > 0 && port < 6)
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mask |= QCA8K_PORT_STATUS_LINK_AUTO;
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if (enable)
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regmap_set_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask);
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else
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regmap_clear_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask);
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}
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void qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset,
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uint8_t *data)
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{
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struct qca8k_priv *priv = ds->priv;
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int i;
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if (stringset != ETH_SS_STATS)
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return;
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for (i = 0; i < priv->info->mib_count; i++)
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strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
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ETH_GSTRING_LEN);
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}
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void qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
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uint64_t *data)
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{
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struct qca8k_priv *priv = ds->priv;
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const struct qca8k_mib_desc *mib;
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u32 reg, i, val;
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u32 hi = 0;
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int ret;
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if (priv->mgmt_master && priv->info->ops->autocast_mib &&
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priv->info->ops->autocast_mib(ds, port, data) > 0)
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return;
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for (i = 0; i < priv->info->mib_count; i++) {
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mib = &ar8327_mib[i];
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reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
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ret = qca8k_read(priv, reg, &val);
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if (ret < 0)
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continue;
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if (mib->size == 2) {
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ret = qca8k_read(priv, reg + 4, &hi);
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if (ret < 0)
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continue;
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}
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data[i] = val;
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if (mib->size == 2)
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data[i] |= (u64)hi << 32;
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}
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}
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int qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset)
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{
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struct qca8k_priv *priv = ds->priv;
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if (sset != ETH_SS_STATS)
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return 0;
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return priv->info->mib_count;
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}
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int qca8k_set_mac_eee(struct dsa_switch *ds, int port,
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struct ethtool_eee *eee)
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{
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u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
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struct qca8k_priv *priv = ds->priv;
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u32 reg;
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int ret;
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mutex_lock(&priv->reg_mutex);
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ret = qca8k_read(priv, QCA8K_REG_EEE_CTRL, ®);
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if (ret < 0)
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goto exit;
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if (eee->eee_enabled)
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reg |= lpi_en;
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else
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reg &= ~lpi_en;
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ret = qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
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exit:
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mutex_unlock(&priv->reg_mutex);
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return ret;
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}
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int qca8k_get_mac_eee(struct dsa_switch *ds, int port,
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struct ethtool_eee *e)
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{
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/* Nothing to do on the port's MAC */
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return 0;
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}
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