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460d0d4448
The PLL2 on the A10 and later SoCs is the clock used for all the audio related operations. This clock has a somewhat complex output tree, with three outputs (2X, 4X and 8X) with a fixed divider from the base clock, and an output (1X) with a post divider. However, we can simplify things since the 1X divider can be fixed, and we end up by having a base clock not exposed to any device (or at least directly, since the 4X output doesn't have any divider), and 4 fixed divider clocks that will be exposed. This clock seems to have been introduced, at least in this form, in the revision B of the A10, but we don't have any information on the clock used on the revision A. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
18 lines
404 B
Makefile
18 lines
404 B
Makefile
#
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# Makefile for sunxi specific clk
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#
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obj-y += clk-sunxi.o clk-factors.o
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obj-y += clk-a10-hosc.o
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obj-y += clk-a10-pll2.o
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obj-y += clk-a20-gmac.o
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obj-y += clk-mod0.o
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obj-y += clk-simple-gates.o
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obj-y += clk-sun8i-mbus.o
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obj-y += clk-sun9i-core.o
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obj-y += clk-sun9i-mmc.o
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obj-y += clk-usb.o
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obj-$(CONFIG_MFD_SUN6I_PRCM) += \
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clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
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clk-sun8i-apb0.o
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