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458e999eb1
Erratum id: i608 RTA (Retention Till Access) feature is not supported and leads to device stability issues when enabled. This impacts modules with embedded memories on OMAP3630 Workaround is to disable RTA on boot and coming out of core off. For disabling RTA coming out of off mode, we do this by overriding the restore pointer for 3630 as the first point of entry before caches are touched and is common for GP and HS devices. To disable earlier than this could be possible by modifying the PPA for HS devices, but not for GP devices. Cc: Kevin Hilman <khilman@deeprootsystems.com> Cc: Tony Lindgren <tony@atomide.com> Acked-by: Jean Pihet <j-pihet@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [ambresh@ti.com: co-developer] Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
97 lines
3 KiB
C
97 lines
3 KiB
C
/*
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* OMAP2/3 Power Management Routines
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*
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* Copyright (C) 2008 Nokia Corporation
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* Jouni Hogander
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_PM_H
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#define __ARCH_ARM_MACH_OMAP2_PM_H
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#include <plat/powerdomain.h>
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extern void *omap3_secure_ram_storage;
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extern void omap3_pm_off_mode_enable(int);
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extern void omap_sram_idle(void);
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extern int omap3_can_sleep(void);
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extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
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extern int omap3_idle_init(void);
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struct cpuidle_params {
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u8 valid;
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u32 sleep_latency;
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u32 wake_latency;
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u32 threshold;
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};
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#if defined(CONFIG_PM) && defined(CONFIG_CPU_IDLE)
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extern void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params);
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#else
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static
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inline void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
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{
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}
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#endif
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extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
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extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
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extern u32 wakeup_timer_seconds;
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extern u32 wakeup_timer_milliseconds;
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extern struct omap_dm_timer *gptimer_wakeup;
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#ifdef CONFIG_PM_DEBUG
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extern void omap2_pm_dump(int mode, int resume, unsigned int us);
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extern void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds);
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extern int omap2_pm_debug;
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extern u32 enable_off_mode;
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extern u32 sleep_while_idle;
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#else
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#define omap2_pm_dump(mode, resume, us) do {} while (0);
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#define omap2_pm_wakeup_on_timer(seconds, milliseconds) do {} while (0);
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#define omap2_pm_debug 0
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#define enable_off_mode 0
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#define sleep_while_idle 0
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#endif
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#if defined(CONFIG_CPU_IDLE)
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extern void omap3_cpuidle_update_states(void);
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#endif
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#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
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extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
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extern int pm_dbg_regset_save(int reg_set);
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extern int pm_dbg_regset_init(int reg_set);
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#else
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#define pm_dbg_update_time(pwrdm, prev) do {} while (0);
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#define pm_dbg_regset_save(reg_set) do {} while (0);
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#define pm_dbg_regset_init(reg_set) do {} while (0);
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#endif /* CONFIG_PM_DEBUG */
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extern void omap24xx_idle_loop_suspend(void);
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extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
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void __iomem *sdrc_power);
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extern void omap34xx_cpu_suspend(u32 *addr, int save_state);
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extern void save_secure_ram_context(u32 *addr);
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extern void omap3_save_scratchpad_contents(void);
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extern unsigned int omap24xx_idle_loop_suspend_sz;
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extern unsigned int omap34xx_suspend_sz;
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extern unsigned int save_secure_ram_context_sz;
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extern unsigned int omap24xx_cpu_suspend_sz;
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extern unsigned int omap34xx_cpu_suspend_sz;
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#define PM_RTA_ERRATUM_i608 (1 << 0)
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#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
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extern u16 pm34xx_errata;
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#define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id))
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#else
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#define IS_PM34XX_ERRATUM(id) 0
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#endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
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#endif
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