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453dfcee70
Some configurations (i.e., 64k + LVA/LPA) can tolerate a physical placement of the kernel image outside of the 48-bit addressable region, but given that the loader has no way of knowing whether or not the image in question supports LVA/LPA, it currently has no choice but to place it below the 48-bit mark. Once we add support for LPA2, which allows 52-bit physical and virtual addressing when using 4k or 16k pages, but in way that relies on increasing the number of paging levels, there will be more variety in the configurations that may or may not support this. So redefine bit #3 in the Image header as 'must be placed within 48-bit addressable memory', as this is the current de facto meaning. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20221122170249.2453853-1-ardb@kernel.org Signed-off-by: Will Deacon <will@kernel.org> |
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| .. | ||
| acpi_object_usage.rst | ||
| amu.rst | ||
| arm-acpi.rst | ||
| asymmetric-32bit.rst | ||
| booting.rst | ||
| cpu-feature-registers.rst | ||
| elf_hwcaps.rst | ||
| features.rst | ||
| hugetlbpage.rst | ||
| index.rst | ||
| kasan-offsets.sh | ||
| legacy_instructions.rst | ||
| memory-tagging-extension.rst | ||
| memory.rst | ||
| perf.rst | ||
| pointer-authentication.rst | ||
| silicon-errata.rst | ||
| sme.rst | ||
| sve.rst | ||
| tagged-address-abi.rst | ||
| tagged-pointers.rst | ||