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linux/Documentation/devicetree/bindings/riscv
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Palmer Dabbelt 2524257bce
dt-bindings: Fix phandle-array issues in the idle-states bindings 
As per 39bd2b6a37 ("dt-bindings: Improve phandle-array schemas"), the
phandle-array bindings have been disambiguated.  This fixes the new
RISC-V idle-states bindings to comply with the schema.

Fixes: 1bd524f7e8 ("dt-bindings: Add common bindings for ARM and RISC-V idle states")
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-04-01 15:09:50 -07:00
..
canaan.yaml dt-bindings: add Canaan boards compatible strings 2021-02-22 17:51:06 -08:00
cpus.yaml dt-bindings: Fix phandle-array issues in the idle-states bindings 2022-04-01 15:09:50 -07:00
microchip.yaml dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC 2021-04-26 08:31:30 -07:00
sifive-l2-cache.yaml MAINTAINERS: sifive: drop Yash Shah 2022-02-22 15:15:39 -06:00
sifive.yaml dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched board 2021-01-07 17:37:41 -08:00
starfive.yaml dt-bindings: riscv: add starfive jh7100 bindings 2021-08-04 13:25:28 -07:00