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4440977be1
Rename l5_paging_required() to paging_prepare() and change the interface of the function. This is a preparation for the next patch, which would make the function also allocate memory for the 32-bit trampoline. The function now returns a 128-bit structure. RAX would return trampoline memory address (zero for now) and RDX would indicate if we need to enable 5-level paging. Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> [ Typo fixes and general clarification. ] Cc: Andy Lutomirski <luto@amacapital.net> Cc: Borislav Petkov <bp@suse.de> Cc: Cyrill Gorcunov <gorcunov@openvz.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Matthew Wilcox <willy@infradead.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mm@kvack.org Link: http://lkml.kernel.org/r/20180209142228.21231-3-kirill.shutemov@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
27 lines
712 B
C
27 lines
712 B
C
#include <asm/processor.h>
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/*
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* __force_order is used by special_insns.h asm code to force instruction
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* serialization.
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*
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* It is not referenced from the code, but GCC < 5 with -fPIE would fail
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* due to an undefined symbol. Define it to make these ancient GCCs work.
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*/
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unsigned long __force_order;
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struct paging_config {
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unsigned long trampoline_start;
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unsigned long l5_required;
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};
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struct paging_config paging_prepare(void)
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{
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struct paging_config paging_config = {};
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/* Check if LA57 is desired and supported */
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if (IS_ENABLED(CONFIG_X86_5LEVEL) && native_cpuid_eax(0) >= 7 &&
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(native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31))))
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paging_config.l5_required = 1;
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return paging_config;
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}
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