Ido Shamay 43c816c67a net/mlx4_core: Cache line EQE size support ... Enable mlx4 interrupt handler to work with EQE stride feature, The feature may be enabled when cache line is bigger than 64B. The EQE size will then be the cache line size, and the context segment resides in [0-31] offset. Signed-off-by: Ido Shamay <idos@mellanox.com> Signed-off-by: Jack Morgenstein <jackm@dev.mellanox.co.il> Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>		2014-09-19 17:30:10 -04:00
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mlx4	net/mlx4_core: Cache line EQE size support	2014-09-19 17:30:10 -04:00
mlx5/core	Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next	2014-08-06 09:38:14 -07:00
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