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435037c630
No test hardware and no (apparent) users. These boards seem very similar to the DB1500, so if required support can be brought back again (I have datasheets) but then with dedicated board code, not tacked on to DB1000 support. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2864/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
250 lines
6.9 KiB
C
250 lines
6.9 KiB
C
/*
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* DBAu1xxx board platform device registration
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*
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* Copyright (C) 2009 Manuel Lauss
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-au1x00/au1000_dma.h>
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#include <asm/mach-db1x00/bcsr.h>
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#include "../platform.h"
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struct pci_dev;
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/* DB1xxx PCMCIA interrupt sources:
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* CD0/1 GPIO0/3
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* STSCHG0/1 GPIO1/4
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* CARD0/1 GPIO2/5
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* Db1550: 0/1, 21/22, 3/5
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*/
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#define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT)
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#if defined(CONFIG_MIPS_DB1000)
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#define DB1XXX_PCMCIA_CD0 AU1000_GPIO0_INT
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#define DB1XXX_PCMCIA_STSCHG0 AU1000_GPIO1_INT
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#define DB1XXX_PCMCIA_CARD0 AU1000_GPIO2_INT
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#define DB1XXX_PCMCIA_CD1 AU1000_GPIO3_INT
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#define DB1XXX_PCMCIA_STSCHG1 AU1000_GPIO4_INT
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#define DB1XXX_PCMCIA_CARD1 AU1000_GPIO5_INT
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#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
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#elif defined(CONFIG_MIPS_DB1100)
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#define DB1XXX_PCMCIA_CD0 AU1100_GPIO0_INT
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#define DB1XXX_PCMCIA_STSCHG0 AU1100_GPIO1_INT
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#define DB1XXX_PCMCIA_CARD0 AU1100_GPIO2_INT
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#define DB1XXX_PCMCIA_CD1 AU1100_GPIO3_INT
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#define DB1XXX_PCMCIA_STSCHG1 AU1100_GPIO4_INT
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#define DB1XXX_PCMCIA_CARD1 AU1100_GPIO5_INT
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#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
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#elif defined(CONFIG_MIPS_DB1500)
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#define DB1XXX_PCMCIA_CD0 AU1500_GPIO0_INT
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#define DB1XXX_PCMCIA_STSCHG0 AU1500_GPIO1_INT
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#define DB1XXX_PCMCIA_CARD0 AU1500_GPIO2_INT
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#define DB1XXX_PCMCIA_CD1 AU1500_GPIO3_INT
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#define DB1XXX_PCMCIA_STSCHG1 AU1500_GPIO4_INT
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#define DB1XXX_PCMCIA_CARD1 AU1500_GPIO5_INT
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#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */
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#elif defined(CONFIG_MIPS_DB1550)
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#define DB1XXX_PCMCIA_CD0 AU1550_GPIO0_INT
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#define DB1XXX_PCMCIA_STSCHG0 AU1550_GPIO21_INT
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#define DB1XXX_PCMCIA_CARD0 AU1550_GPIO3_INT
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#define DB1XXX_PCMCIA_CD1 AU1550_GPIO1_INT
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#define DB1XXX_PCMCIA_STSCHG1 AU1550_GPIO22_INT
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#define DB1XXX_PCMCIA_CARD1 AU1550_GPIO5_INT
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#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */
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#endif
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#ifdef CONFIG_PCI
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#ifdef CONFIG_MIPS_DB1500
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static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
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{
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if ((slot < 12) || (slot > 13) || pin == 0)
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return -1;
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if (slot == 12)
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return (pin == 1) ? AU1500_PCI_INTA : 0xff;
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if (slot == 13) {
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switch (pin) {
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case 1: return AU1500_PCI_INTA;
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case 2: return AU1500_PCI_INTB;
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case 3: return AU1500_PCI_INTC;
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case 4: return AU1500_PCI_INTD;
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}
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}
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return -1;
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}
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#endif
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#ifdef CONFIG_MIPS_DB1550
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static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
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{
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if ((slot < 11) || (slot > 13) || pin == 0)
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return -1;
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if (slot == 11)
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return (pin == 1) ? AU1550_PCI_INTC : 0xff;
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if (slot == 12) {
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switch (pin) {
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case 1: return AU1550_PCI_INTB;
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case 2: return AU1550_PCI_INTC;
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case 3: return AU1550_PCI_INTD;
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case 4: return AU1550_PCI_INTA;
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}
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}
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if (slot == 13) {
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switch (pin) {
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case 1: return AU1550_PCI_INTA;
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case 2: return AU1550_PCI_INTB;
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case 3: return AU1550_PCI_INTC;
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case 4: return AU1550_PCI_INTD;
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}
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}
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return -1;
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}
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#endif
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static struct resource alchemy_pci_host_res[] = {
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[0] = {
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.start = AU1500_PCI_PHYS_ADDR,
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.end = AU1500_PCI_PHYS_ADDR + 0xfff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct alchemy_pci_platdata db1xxx_pci_pd = {
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.board_map_irq = db1xxx_map_pci_irq,
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};
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static struct platform_device db1xxx_pci_host_dev = {
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.dev.platform_data = &db1xxx_pci_pd,
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.name = "alchemy-pci",
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.id = 0,
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.num_resources = ARRAY_SIZE(alchemy_pci_host_res),
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.resource = alchemy_pci_host_res,
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};
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static int __init db15x0_pci_init(void)
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{
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return platform_device_register(&db1xxx_pci_host_dev);
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}
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/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
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arch_initcall(db15x0_pci_init);
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#endif
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#ifdef CONFIG_MIPS_DB1100
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static struct resource au1100_lcd_resources[] = {
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[0] = {
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.start = AU1100_LCD_PHYS_ADDR,
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.end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = AU1100_LCD_INT,
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.end = AU1100_LCD_INT,
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.flags = IORESOURCE_IRQ,
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}
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};
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static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
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static struct platform_device au1100_lcd_device = {
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.name = "au1100-lcd",
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.id = 0,
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.dev = {
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.dma_mask = &au1100_lcd_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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.num_resources = ARRAY_SIZE(au1100_lcd_resources),
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.resource = au1100_lcd_resources,
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};
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#endif
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static struct resource alchemy_ac97c_res[] = {
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[0] = {
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.start = AU1000_AC97_PHYS_ADDR,
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.end = AU1000_AC97_PHYS_ADDR + 0xfff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = DMA_ID_AC97C_TX,
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.end = DMA_ID_AC97C_TX,
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.flags = IORESOURCE_DMA,
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},
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[2] = {
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.start = DMA_ID_AC97C_RX,
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.end = DMA_ID_AC97C_RX,
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.flags = IORESOURCE_DMA,
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},
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};
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static struct platform_device alchemy_ac97c_dev = {
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.name = "alchemy-ac97c",
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.id = -1,
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.resource = alchemy_ac97c_res,
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.num_resources = ARRAY_SIZE(alchemy_ac97c_res),
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};
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static struct platform_device alchemy_ac97c_dma_dev = {
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.name = "alchemy-pcm-dma",
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.id = 0,
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};
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static struct platform_device db1x00_codec_dev = {
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.name = "ac97-codec",
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.id = -1,
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};
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static struct platform_device db1x00_audio_dev = {
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.name = "db1000-audio",
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};
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static int __init db1xxx_dev_init(void)
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{
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db1x_register_pcmcia_socket(
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AU1000_PCMCIA_ATTR_PHYS_ADDR,
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AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
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AU1000_PCMCIA_MEM_PHYS_ADDR,
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AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
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AU1000_PCMCIA_IO_PHYS_ADDR,
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AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
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DB1XXX_PCMCIA_CARD0, DB1XXX_PCMCIA_CD0,
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/*DB1XXX_PCMCIA_STSCHG0*/0, 0, 0);
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db1x_register_pcmcia_socket(
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AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
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AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
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AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
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AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
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AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
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AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
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DB1XXX_PCMCIA_CARD1, DB1XXX_PCMCIA_CD1,
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/*DB1XXX_PCMCIA_STSCHG1*/0, 0, 1);
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#ifdef CONFIG_MIPS_DB1100
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platform_device_register(&au1100_lcd_device);
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#endif
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platform_device_register(&db1x00_codec_dev);
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platform_device_register(&alchemy_ac97c_dma_dev);
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platform_device_register(&alchemy_ac97c_dev);
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platform_device_register(&db1x00_audio_dev);
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db1x_register_norflash(BOARD_FLASH_SIZE, 4 /* 32bit */, F_SWAPPED);
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return 0;
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}
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device_initcall(db1xxx_dev_init);
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