mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-08-05 16:54:27 +00:00
41d65207de
Today we get the following code generation for atomic operations: c001bb2c: 39 20 00 01 li r9,1 c001bb30: 7d 40 18 28 lwarx r10,0,r3 c001bb34: 7d 09 50 50 subf r8,r9,r10 c001bb38: 7d 00 19 2d stwcx. r8,0,r3 c001c7a8: 39 40 00 01 li r10,1 c001c7ac: 7d 00 18 28 lwarx r8,0,r3 c001c7b0: 7c ea 42 14 add r7,r10,r8 c001c7b4: 7c e0 19 2d stwcx. r7,0,r3 By allowing GCC to choose between immediate or regular operation, we get: c001bb2c: 7d 20 18 28 lwarx r9,0,r3 c001bb30: 39 49 ff ff addi r10,r9,-1 c001bb34: 7d 40 19 2d stwcx. r10,0,r3 -- c001c7a4: 7d 40 18 28 lwarx r10,0,r3 c001c7a8: 39 0a 00 01 addi r8,r10,1 c001c7ac: 7d 00 19 2d stwcx. r8,0,r3 For "and", the dot form has to be used because "andi" doesn't exist. For logical operations we use unsigned 16 bits immediate. For arithmetic operations we use signed 16 bits immediate. On pmac32_defconfig, it reduces the text by approx another 8 kbytes. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Acked-by: Segher Boessenkool <segher@kernel.crashing.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/2ec558d44db8045752fe9dbd29c9ba84bab6030b.1632236981.git.christophe.leroy@csgroup.eu
583 lines
14 KiB
C
583 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_ATOMIC_H_
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#define _ASM_POWERPC_ATOMIC_H_
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/*
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* PowerPC atomic operations
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*/
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#ifdef __KERNEL__
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#include <linux/types.h>
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#include <asm/cmpxchg.h>
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#include <asm/barrier.h>
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#include <asm/asm-const.h>
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/*
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* Since *_return_relaxed and {cmp}xchg_relaxed are implemented with
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* a "bne-" instruction at the end, so an isync is enough as a acquire barrier
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* on the platform without lwsync.
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*/
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#define __atomic_acquire_fence() \
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__asm__ __volatile__(PPC_ACQUIRE_BARRIER "" : : : "memory")
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#define __atomic_release_fence() \
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__asm__ __volatile__(PPC_RELEASE_BARRIER "" : : : "memory")
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static __inline__ int arch_atomic_read(const atomic_t *v)
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{
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int t;
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__asm__ __volatile__("lwz%U1%X1 %0,%1" : "=r"(t) : "m<>"(v->counter));
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return t;
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}
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static __inline__ void arch_atomic_set(atomic_t *v, int i)
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{
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__asm__ __volatile__("stw%U0%X0 %1,%0" : "=m<>"(v->counter) : "r"(i));
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}
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#define ATOMIC_OP(op, asm_op, suffix, sign, ...) \
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static __inline__ void arch_atomic_##op(int a, atomic_t *v) \
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{ \
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int t; \
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\
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__asm__ __volatile__( \
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"1: lwarx %0,0,%3 # atomic_" #op "\n" \
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#asm_op "%I2" suffix " %0,%0,%2\n" \
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" stwcx. %0,0,%3 \n" \
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" bne- 1b\n" \
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: "=&r" (t), "+m" (v->counter) \
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: "r"#sign (a), "r" (&v->counter) \
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: "cc", ##__VA_ARGS__); \
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} \
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#define ATOMIC_OP_RETURN_RELAXED(op, asm_op, suffix, sign, ...) \
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static inline int arch_atomic_##op##_return_relaxed(int a, atomic_t *v) \
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{ \
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int t; \
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\
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__asm__ __volatile__( \
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"1: lwarx %0,0,%3 # atomic_" #op "_return_relaxed\n" \
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#asm_op "%I2" suffix " %0,%0,%2\n" \
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" stwcx. %0,0,%3\n" \
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" bne- 1b\n" \
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: "=&r" (t), "+m" (v->counter) \
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: "r"#sign (a), "r" (&v->counter) \
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: "cc", ##__VA_ARGS__); \
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\
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return t; \
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}
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#define ATOMIC_FETCH_OP_RELAXED(op, asm_op, suffix, sign, ...) \
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static inline int arch_atomic_fetch_##op##_relaxed(int a, atomic_t *v) \
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{ \
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int res, t; \
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\
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__asm__ __volatile__( \
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"1: lwarx %0,0,%4 # atomic_fetch_" #op "_relaxed\n" \
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#asm_op "%I3" suffix " %1,%0,%3\n" \
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" stwcx. %1,0,%4\n" \
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" bne- 1b\n" \
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: "=&r" (res), "=&r" (t), "+m" (v->counter) \
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: "r"#sign (a), "r" (&v->counter) \
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: "cc", ##__VA_ARGS__); \
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\
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return res; \
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}
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#define ATOMIC_OPS(op, asm_op, suffix, sign, ...) \
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ATOMIC_OP(op, asm_op, suffix, sign, ##__VA_ARGS__) \
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ATOMIC_OP_RETURN_RELAXED(op, asm_op, suffix, sign, ##__VA_ARGS__)\
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ATOMIC_FETCH_OP_RELAXED(op, asm_op, suffix, sign, ##__VA_ARGS__)
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ATOMIC_OPS(add, add, "c", I, "xer")
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ATOMIC_OPS(sub, sub, "c", I, "xer")
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#define arch_atomic_add_return_relaxed arch_atomic_add_return_relaxed
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#define arch_atomic_sub_return_relaxed arch_atomic_sub_return_relaxed
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#define arch_atomic_fetch_add_relaxed arch_atomic_fetch_add_relaxed
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#define arch_atomic_fetch_sub_relaxed arch_atomic_fetch_sub_relaxed
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(op, asm_op, suffix, sign) \
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ATOMIC_OP(op, asm_op, suffix, sign) \
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ATOMIC_FETCH_OP_RELAXED(op, asm_op, suffix, sign)
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ATOMIC_OPS(and, and, ".", K)
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ATOMIC_OPS(or, or, "", K)
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ATOMIC_OPS(xor, xor, "", K)
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#define arch_atomic_fetch_and_relaxed arch_atomic_fetch_and_relaxed
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#define arch_atomic_fetch_or_relaxed arch_atomic_fetch_or_relaxed
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#define arch_atomic_fetch_xor_relaxed arch_atomic_fetch_xor_relaxed
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP_RELAXED
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#undef ATOMIC_OP_RETURN_RELAXED
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#undef ATOMIC_OP
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static __inline__ void arch_atomic_inc(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_inc\n\
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addic %0,%0,1\n"
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" stwcx. %0,0,%2 \n\
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bne- 1b"
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: "=&r" (t), "+m" (v->counter)
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: "r" (&v->counter)
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: "cc", "xer");
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}
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#define arch_atomic_inc arch_atomic_inc
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static __inline__ int arch_atomic_inc_return_relaxed(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_inc_return_relaxed\n"
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" addic %0,%0,1\n"
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" stwcx. %0,0,%2\n"
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" bne- 1b"
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: "=&r" (t), "+m" (v->counter)
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: "r" (&v->counter)
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: "cc", "xer");
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return t;
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}
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static __inline__ void arch_atomic_dec(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_dec\n\
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addic %0,%0,-1\n"
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" stwcx. %0,0,%2\n\
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bne- 1b"
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: "=&r" (t), "+m" (v->counter)
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: "r" (&v->counter)
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: "cc", "xer");
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}
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#define arch_atomic_dec arch_atomic_dec
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static __inline__ int arch_atomic_dec_return_relaxed(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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"1: lwarx %0,0,%2 # atomic_dec_return_relaxed\n"
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" addic %0,%0,-1\n"
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" stwcx. %0,0,%2\n"
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" bne- 1b"
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: "=&r" (t), "+m" (v->counter)
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: "r" (&v->counter)
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: "cc", "xer");
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return t;
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}
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#define arch_atomic_inc_return_relaxed arch_atomic_inc_return_relaxed
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#define arch_atomic_dec_return_relaxed arch_atomic_dec_return_relaxed
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#define arch_atomic_cmpxchg(v, o, n) \
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(arch_cmpxchg(&((v)->counter), (o), (n)))
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#define arch_atomic_cmpxchg_relaxed(v, o, n) \
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arch_cmpxchg_relaxed(&((v)->counter), (o), (n))
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#define arch_atomic_cmpxchg_acquire(v, o, n) \
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arch_cmpxchg_acquire(&((v)->counter), (o), (n))
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#define arch_atomic_xchg(v, new) \
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(arch_xchg(&((v)->counter), new))
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#define arch_atomic_xchg_relaxed(v, new) \
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arch_xchg_relaxed(&((v)->counter), (new))
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/*
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* Don't want to override the generic atomic_try_cmpxchg_acquire, because
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* we add a lock hint to the lwarx, which may not be wanted for the
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* _acquire case (and is not used by the other _acquire variants so it
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* would be a surprise).
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*/
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static __always_inline bool
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arch_atomic_try_cmpxchg_lock(atomic_t *v, int *old, int new)
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{
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int r, o = *old;
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__asm__ __volatile__ (
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"1: lwarx %0,0,%2,%5 # atomic_try_cmpxchg_acquire \n"
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" cmpw 0,%0,%3 \n"
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" bne- 2f \n"
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" stwcx. %4,0,%2 \n"
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" bne- 1b \n"
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"\t" PPC_ACQUIRE_BARRIER " \n"
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"2: \n"
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: "=&r" (r), "+m" (v->counter)
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: "r" (&v->counter), "r" (o), "r" (new), "i" (IS_ENABLED(CONFIG_PPC64) ? 1 : 0)
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: "cr0", "memory");
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if (unlikely(r != o))
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*old = r;
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return likely(r == o);
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}
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/**
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* atomic_fetch_add_unless - add unless the number is a given value
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* @v: pointer of type atomic_t
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* @a: the amount to add to v...
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* @u: ...unless v is equal to u.
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*
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* Atomically adds @a to @v, so long as it was not @u.
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* Returns the old value of @v.
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*/
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static __inline__ int arch_atomic_fetch_add_unless(atomic_t *v, int a, int u)
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{
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int t;
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__asm__ __volatile__ (
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PPC_ATOMIC_ENTRY_BARRIER
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"1: lwarx %0,0,%1 # atomic_fetch_add_unless\n\
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cmpw 0,%0,%3 \n\
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beq 2f \n\
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add%I2c %0,%0,%2 \n"
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" stwcx. %0,0,%1 \n\
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bne- 1b \n"
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PPC_ATOMIC_EXIT_BARRIER
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" sub%I2c %0,%0,%2 \n\
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2:"
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: "=&r" (t)
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: "r" (&v->counter), "rI" (a), "r" (u)
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: "cc", "memory", "xer");
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return t;
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}
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#define arch_atomic_fetch_add_unless arch_atomic_fetch_add_unless
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/**
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* atomic_inc_not_zero - increment unless the number is zero
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* @v: pointer of type atomic_t
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*
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* Atomically increments @v by 1, so long as @v is non-zero.
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* Returns non-zero if @v was non-zero, and zero otherwise.
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*/
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static __inline__ int arch_atomic_inc_not_zero(atomic_t *v)
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{
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int t1, t2;
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__asm__ __volatile__ (
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PPC_ATOMIC_ENTRY_BARRIER
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"1: lwarx %0,0,%2 # atomic_inc_not_zero\n\
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cmpwi 0,%0,0\n\
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beq- 2f\n\
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addic %1,%0,1\n"
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" stwcx. %1,0,%2\n\
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bne- 1b\n"
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PPC_ATOMIC_EXIT_BARRIER
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"\n\
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2:"
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: "=&r" (t1), "=&r" (t2)
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: "r" (&v->counter)
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: "cc", "xer", "memory");
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return t1;
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}
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#define arch_atomic_inc_not_zero(v) arch_atomic_inc_not_zero((v))
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/*
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* Atomically test *v and decrement if it is greater than 0.
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* The function returns the old value of *v minus 1, even if
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* the atomic variable, v, was not decremented.
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*/
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static __inline__ int arch_atomic_dec_if_positive(atomic_t *v)
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{
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int t;
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__asm__ __volatile__(
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PPC_ATOMIC_ENTRY_BARRIER
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"1: lwarx %0,0,%1 # atomic_dec_if_positive\n\
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cmpwi %0,1\n\
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addi %0,%0,-1\n\
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blt- 2f\n"
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" stwcx. %0,0,%1\n\
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bne- 1b"
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PPC_ATOMIC_EXIT_BARRIER
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"\n\
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2:" : "=&b" (t)
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: "r" (&v->counter)
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: "cc", "memory");
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return t;
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}
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#define arch_atomic_dec_if_positive arch_atomic_dec_if_positive
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#ifdef __powerpc64__
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#define ATOMIC64_INIT(i) { (i) }
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static __inline__ s64 arch_atomic64_read(const atomic64_t *v)
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{
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s64 t;
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__asm__ __volatile__("ld%U1%X1 %0,%1" : "=r"(t) : "m<>"(v->counter));
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return t;
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}
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static __inline__ void arch_atomic64_set(atomic64_t *v, s64 i)
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{
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__asm__ __volatile__("std%U0%X0 %1,%0" : "=m<>"(v->counter) : "r"(i));
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}
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#define ATOMIC64_OP(op, asm_op) \
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static __inline__ void arch_atomic64_##op(s64 a, atomic64_t *v) \
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{ \
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s64 t; \
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\
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__asm__ __volatile__( \
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"1: ldarx %0,0,%3 # atomic64_" #op "\n" \
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#asm_op " %0,%2,%0\n" \
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" stdcx. %0,0,%3 \n" \
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" bne- 1b\n" \
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: "=&r" (t), "+m" (v->counter) \
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: "r" (a), "r" (&v->counter) \
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: "cc"); \
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}
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#define ATOMIC64_OP_RETURN_RELAXED(op, asm_op) \
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static inline s64 \
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arch_atomic64_##op##_return_relaxed(s64 a, atomic64_t *v) \
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{ \
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s64 t; \
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\
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__asm__ __volatile__( \
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"1: ldarx %0,0,%3 # atomic64_" #op "_return_relaxed\n" \
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#asm_op " %0,%2,%0\n" \
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" stdcx. %0,0,%3\n" \
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" bne- 1b\n" \
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: "=&r" (t), "+m" (v->counter) \
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: "r" (a), "r" (&v->counter) \
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: "cc"); \
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\
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return t; \
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}
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#define ATOMIC64_FETCH_OP_RELAXED(op, asm_op) \
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static inline s64 \
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arch_atomic64_fetch_##op##_relaxed(s64 a, atomic64_t *v) \
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{ \
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s64 res, t; \
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\
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__asm__ __volatile__( \
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"1: ldarx %0,0,%4 # atomic64_fetch_" #op "_relaxed\n" \
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#asm_op " %1,%3,%0\n" \
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" stdcx. %1,0,%4\n" \
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" bne- 1b\n" \
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: "=&r" (res), "=&r" (t), "+m" (v->counter) \
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: "r" (a), "r" (&v->counter) \
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: "cc"); \
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\
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return res; \
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}
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#define ATOMIC64_OPS(op, asm_op) \
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ATOMIC64_OP(op, asm_op) \
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ATOMIC64_OP_RETURN_RELAXED(op, asm_op) \
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ATOMIC64_FETCH_OP_RELAXED(op, asm_op)
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ATOMIC64_OPS(add, add)
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ATOMIC64_OPS(sub, subf)
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#define arch_atomic64_add_return_relaxed arch_atomic64_add_return_relaxed
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#define arch_atomic64_sub_return_relaxed arch_atomic64_sub_return_relaxed
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#define arch_atomic64_fetch_add_relaxed arch_atomic64_fetch_add_relaxed
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#define arch_atomic64_fetch_sub_relaxed arch_atomic64_fetch_sub_relaxed
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#undef ATOMIC64_OPS
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#define ATOMIC64_OPS(op, asm_op) \
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ATOMIC64_OP(op, asm_op) \
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ATOMIC64_FETCH_OP_RELAXED(op, asm_op)
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ATOMIC64_OPS(and, and)
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ATOMIC64_OPS(or, or)
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ATOMIC64_OPS(xor, xor)
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#define arch_atomic64_fetch_and_relaxed arch_atomic64_fetch_and_relaxed
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#define arch_atomic64_fetch_or_relaxed arch_atomic64_fetch_or_relaxed
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#define arch_atomic64_fetch_xor_relaxed arch_atomic64_fetch_xor_relaxed
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#undef ATOPIC64_OPS
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#undef ATOMIC64_FETCH_OP_RELAXED
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#undef ATOMIC64_OP_RETURN_RELAXED
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#undef ATOMIC64_OP
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static __inline__ void arch_atomic64_inc(atomic64_t *v)
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{
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s64 t;
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__asm__ __volatile__(
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"1: ldarx %0,0,%2 # atomic64_inc\n\
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addic %0,%0,1\n\
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stdcx. %0,0,%2 \n\
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bne- 1b"
|
|
: "=&r" (t), "+m" (v->counter)
|
|
: "r" (&v->counter)
|
|
: "cc", "xer");
|
|
}
|
|
#define arch_atomic64_inc arch_atomic64_inc
|
|
|
|
static __inline__ s64 arch_atomic64_inc_return_relaxed(atomic64_t *v)
|
|
{
|
|
s64 t;
|
|
|
|
__asm__ __volatile__(
|
|
"1: ldarx %0,0,%2 # atomic64_inc_return_relaxed\n"
|
|
" addic %0,%0,1\n"
|
|
" stdcx. %0,0,%2\n"
|
|
" bne- 1b"
|
|
: "=&r" (t), "+m" (v->counter)
|
|
: "r" (&v->counter)
|
|
: "cc", "xer");
|
|
|
|
return t;
|
|
}
|
|
|
|
static __inline__ void arch_atomic64_dec(atomic64_t *v)
|
|
{
|
|
s64 t;
|
|
|
|
__asm__ __volatile__(
|
|
"1: ldarx %0,0,%2 # atomic64_dec\n\
|
|
addic %0,%0,-1\n\
|
|
stdcx. %0,0,%2\n\
|
|
bne- 1b"
|
|
: "=&r" (t), "+m" (v->counter)
|
|
: "r" (&v->counter)
|
|
: "cc", "xer");
|
|
}
|
|
#define arch_atomic64_dec arch_atomic64_dec
|
|
|
|
static __inline__ s64 arch_atomic64_dec_return_relaxed(atomic64_t *v)
|
|
{
|
|
s64 t;
|
|
|
|
__asm__ __volatile__(
|
|
"1: ldarx %0,0,%2 # atomic64_dec_return_relaxed\n"
|
|
" addic %0,%0,-1\n"
|
|
" stdcx. %0,0,%2\n"
|
|
" bne- 1b"
|
|
: "=&r" (t), "+m" (v->counter)
|
|
: "r" (&v->counter)
|
|
: "cc", "xer");
|
|
|
|
return t;
|
|
}
|
|
|
|
#define arch_atomic64_inc_return_relaxed arch_atomic64_inc_return_relaxed
|
|
#define arch_atomic64_dec_return_relaxed arch_atomic64_dec_return_relaxed
|
|
|
|
/*
|
|
* Atomically test *v and decrement if it is greater than 0.
|
|
* The function returns the old value of *v minus 1.
|
|
*/
|
|
static __inline__ s64 arch_atomic64_dec_if_positive(atomic64_t *v)
|
|
{
|
|
s64 t;
|
|
|
|
__asm__ __volatile__(
|
|
PPC_ATOMIC_ENTRY_BARRIER
|
|
"1: ldarx %0,0,%1 # atomic64_dec_if_positive\n\
|
|
addic. %0,%0,-1\n\
|
|
blt- 2f\n\
|
|
stdcx. %0,0,%1\n\
|
|
bne- 1b"
|
|
PPC_ATOMIC_EXIT_BARRIER
|
|
"\n\
|
|
2:" : "=&r" (t)
|
|
: "r" (&v->counter)
|
|
: "cc", "xer", "memory");
|
|
|
|
return t;
|
|
}
|
|
#define arch_atomic64_dec_if_positive arch_atomic64_dec_if_positive
|
|
|
|
#define arch_atomic64_cmpxchg(v, o, n) \
|
|
(arch_cmpxchg(&((v)->counter), (o), (n)))
|
|
#define arch_atomic64_cmpxchg_relaxed(v, o, n) \
|
|
arch_cmpxchg_relaxed(&((v)->counter), (o), (n))
|
|
#define arch_atomic64_cmpxchg_acquire(v, o, n) \
|
|
arch_cmpxchg_acquire(&((v)->counter), (o), (n))
|
|
|
|
#define arch_atomic64_xchg(v, new) \
|
|
(arch_xchg(&((v)->counter), new))
|
|
#define arch_atomic64_xchg_relaxed(v, new) \
|
|
arch_xchg_relaxed(&((v)->counter), (new))
|
|
|
|
/**
|
|
* atomic64_fetch_add_unless - add unless the number is a given value
|
|
* @v: pointer of type atomic64_t
|
|
* @a: the amount to add to v...
|
|
* @u: ...unless v is equal to u.
|
|
*
|
|
* Atomically adds @a to @v, so long as it was not @u.
|
|
* Returns the old value of @v.
|
|
*/
|
|
static __inline__ s64 arch_atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u)
|
|
{
|
|
s64 t;
|
|
|
|
__asm__ __volatile__ (
|
|
PPC_ATOMIC_ENTRY_BARRIER
|
|
"1: ldarx %0,0,%1 # atomic64_fetch_add_unless\n\
|
|
cmpd 0,%0,%3 \n\
|
|
beq 2f \n\
|
|
add %0,%2,%0 \n"
|
|
" stdcx. %0,0,%1 \n\
|
|
bne- 1b \n"
|
|
PPC_ATOMIC_EXIT_BARRIER
|
|
" subf %0,%2,%0 \n\
|
|
2:"
|
|
: "=&r" (t)
|
|
: "r" (&v->counter), "r" (a), "r" (u)
|
|
: "cc", "memory");
|
|
|
|
return t;
|
|
}
|
|
#define arch_atomic64_fetch_add_unless arch_atomic64_fetch_add_unless
|
|
|
|
/**
|
|
* atomic_inc64_not_zero - increment unless the number is zero
|
|
* @v: pointer of type atomic64_t
|
|
*
|
|
* Atomically increments @v by 1, so long as @v is non-zero.
|
|
* Returns non-zero if @v was non-zero, and zero otherwise.
|
|
*/
|
|
static __inline__ int arch_atomic64_inc_not_zero(atomic64_t *v)
|
|
{
|
|
s64 t1, t2;
|
|
|
|
__asm__ __volatile__ (
|
|
PPC_ATOMIC_ENTRY_BARRIER
|
|
"1: ldarx %0,0,%2 # atomic64_inc_not_zero\n\
|
|
cmpdi 0,%0,0\n\
|
|
beq- 2f\n\
|
|
addic %1,%0,1\n\
|
|
stdcx. %1,0,%2\n\
|
|
bne- 1b\n"
|
|
PPC_ATOMIC_EXIT_BARRIER
|
|
"\n\
|
|
2:"
|
|
: "=&r" (t1), "=&r" (t2)
|
|
: "r" (&v->counter)
|
|
: "cc", "xer", "memory");
|
|
|
|
return t1 != 0;
|
|
}
|
|
#define arch_atomic64_inc_not_zero(v) arch_atomic64_inc_not_zero((v))
|
|
|
|
#endif /* __powerpc64__ */
|
|
|
|
#endif /* __KERNEL__ */
|
|
#endif /* _ASM_POWERPC_ATOMIC_H_ */
|