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edf7550a1f
The ASPEED SoC must deassert a reset in order to use the ADC peripheral. The device tree bindings are updated to document the resets phandle, and the example is updated to match what is expected for both the reset and clock phandle. Note that the bindings should have always had the reset controller, as the hardware is unusable without it. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
22 lines
678 B
Text
22 lines
678 B
Text
Aspeed ADC
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This device is a 10-bit converter for 16 voltage channels. All inputs are
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single ended.
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Required properties:
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- compatible: Should be "aspeed,ast2400-adc" or "aspeed,ast2500-adc"
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- reg: memory window mapping address and length
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- clocks: Input clock used to derive the sample clock. Expected to be the
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SoC's APB clock.
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- resets: Reset controller phandle
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- #io-channel-cells: Must be set to <1> to indicate channels are selected
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by index.
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Example:
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adc@1e6e9000 {
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compatible = "aspeed,ast2400-adc";
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reg = <0x1e6e9000 0xb0>;
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clocks = <&syscon ASPEED_CLK_APB>;
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resets = <&syscon ASPEED_RESET_ADC>;
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#io-channel-cells = <1>;
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};
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