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bac63d7c5f
The Ka-Ro Electronics tx8p-ml81 is a COM based on the imx8mp SOC. It has 2 GB of ram and 8 GB of eMMC storage on board. Add it to enable boards based on this Module Signed-off-by: Maud Spierings <maudspierings@gocontroll.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
548 lines
13 KiB
Text
548 lines
13 KiB
Text
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2020 Lothar Waßmann <LW@KARO-electronics.de>
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* 2025 Maud Spierings <maudspierings@gocontroll.com>
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*/
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#include "imx8mp.dtsi"
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/ {
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/* PHY regulator */
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regulator-3v3-etn {
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compatible = "regulator-fixed";
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gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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pinctrl-0 = <&pinctrl_reg_3v3_etn>;
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pinctrl-names = "default";
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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regulator-name = "3v3-etn";
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vin-supply = <®_vdd_3v3>;
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};
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};
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&A53_0 {
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cpu-supply = <®_vdd_arm>;
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};
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&A53_1 {
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cpu-supply = <®_vdd_arm>;
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};
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&A53_2 {
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cpu-supply = <®_vdd_arm>;
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};
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&A53_3 {
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cpu-supply = <®_vdd_arm>;
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};
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&eqos {
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assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
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<&clk IMX8MP_CLK_ENET_QOS_TIMER>,
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<&clk IMX8MP_CLK_ENET_QOS>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
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<&clk IMX8MP_SYS_PLL2_100M>,
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<&clk IMX8MP_SYS_PLL2_50M>;
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assigned-clock-rates = <266000000>, <100000000>, <50000000>;
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phy-handle = <ðphy0>;
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phy-mode = "rmii";
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pinctrl-0 = <&pinctrl_eqos>;
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pinctrl-1 = <&pinctrl_eqos_sleep>;
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pinctrl-names = "default", "sleep";
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status = "okay";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&pinctrl_ethphy_rst_b>;
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pinctrl-names = "default";
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reset-delay-us = <25000>;
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reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
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ethphy0: ethernet-phy@0 {
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reg = <0>;
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interrupt-parent = <&gpio4>;
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interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
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clocks = <&clk IMX8MP_CLK_ENET_QOS>;
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pinctrl-0 = <&pinctrl_ethphy_int_b>;
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pinctrl-names = "default";
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smsc,disable-energy-detect;
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};
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};
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};
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&gpio1 {
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gpio-line-names = "SODIMM_152",
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"SODIMM_42",
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"PMIC_WDOG_B SODIMM_153",
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"PMIC_IRQ_B",
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"SODIMM_154",
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"SODIMM_155",
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"SODIMM_156",
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"SODIMM_157",
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"SODIMM_158",
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"SODIMM_159",
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"SODIMM_161",
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"SODIMM_162",
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"SODIMM_34",
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"SODIMM_36",
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"SODIMM_27",
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"SODIMM_28",
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"ENET_MDC",
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"ENET_MDIO",
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"",
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"ENET_XTAL1/CLKIN",
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"ENET_TXD1",
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"ENET_TXD0",
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"ENET_TXEN",
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"ENET_POWER",
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"ENET_COL/CRS_DV",
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"ENET_RXER",
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"ENET_RXD0",
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"ENET_RXD1",
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"",
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"",
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"",
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"";
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};
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&gpio2 {
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gpio-line-names = "",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"SODIMM_51",
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"SODIMM_57",
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"SODIMM_56",
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"SODIMM_52",
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"SODIMM_53",
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"SODIMM_54",
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"SODIMM_55",
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"SODIMM_15",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"";
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};
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&gpio3 {
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gpio-line-names = "",
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"",
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"EMMC_DS",
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"EMMC_DAT5",
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"EMMC_DAT6",
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"EMMC_DAT7",
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"",
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"",
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"",
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"",
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"EMMC_DAT0",
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"EMMC_DAT1",
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"EMMC_DAT2",
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"EMMC_DAT3",
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"",
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"EMMC_DAT4",
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"",
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"EMMC_CLK",
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"EMMC_CMD",
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"SODIMM_75",
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"SODIMM_145",
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"SODIMM_163",
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"SODIMM_164",
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"SODIMM_165",
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"SODIMM_143",
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"SODIMM_144",
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"SODIMM_72",
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"SODIMM_73",
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"SODIMM_74",
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"SODIMM_93",
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"",
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"";
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};
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&gpio4 {
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gpio-line-names = "SODIMM_98",
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"SODIMM_99",
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"SODIMM_100",
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"SODIMM_101",
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"SODIMM_45",
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"SODIMM_43",
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"SODIMM_105",
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"SODIMM_106",
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"SODIMM_107",
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"SODIMM_108",
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"SODIMM_104",
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"SODIMM_103",
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"SODIMM_115",
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"SODIMM_114",
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"SODIMM_113",
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"SODIMM_112",
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"SODIMM_109",
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"SODIMM_110",
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"SODIMM_95",
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"SODIMM_96",
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"SODIMM_97",
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"ENET_nINT",
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"ENET_nRST",
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"SODIMM_84",
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"SODIMM_87",
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"SODIMM_86",
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"SODIMM_85",
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"SODIMM_83",
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"",
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"SODIMM_66",
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"SODIMM_65",
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"";
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};
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&gpio5 {
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gpio-line-names = "",
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"",
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"",
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"SODIMM_76",
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"SODIMM_81",
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"SODIMM_146",
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"SODIMM_48",
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"SODIMM_46",
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"SODIMM_47",
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"SODIMM_44",
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"SODIMM_49",
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"",
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"SODIMM_70",
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"SODIMM_69",
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"PMIC_SCL",
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"PMIC_SDA",
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"SODIMM_41",
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"SODIMM_40",
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"SODIMM_148",
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"SODIMM_149",
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"SODIMM_150",
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"SODIMM_151",
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"SODIMM_60",
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"SODIMM_59",
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"SODIMM_64",
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"SODIMM_63",
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"SODIMM_62",
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"SODIMM_61",
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"SODIMM_68",
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"SODIMM_67",
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"",
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"";
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};
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-0 = <&pinctrl_i2c1>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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pinctrl-names = "default", "gpio";
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scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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pmic@25 {
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compatible = "nxp,pca9450c";
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reg = <0x25>;
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interrupt-parent = <&gpio1>;
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interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
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pinctrl-0 = <&pinctrl_pmic>;
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pinctrl-names = "default";
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regulators {
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reg_vdd_soc: BUCK1 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <900000>;
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regulator-min-microvolt = <805000>;
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regulator-name = "vdd-soc";
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regulator-ramp-delay = <3125>;
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};
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reg_vdd_arm: BUCK2 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <950000>;
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regulator-min-microvolt = <805000>;
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regulator-name = "vdd-core";
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regulator-ramp-delay = <3125>;
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nxp,dvs-run-voltage = <950000>;
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nxp,dvs-standby-voltage = <850000>;
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};
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reg_vdd_3v3: BUCK4 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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regulator-name = "3v3";
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};
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reg_nvcc_nand: BUCK5 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1800000>;
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regulator-min-microvolt = <1800000>;
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regulator-name = "nvcc-nand";
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};
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reg_nvcc_dram: BUCK6 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1100000>;
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regulator-min-microvolt = <1100000>;
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regulator-name = "nvcc-dram";
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};
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reg_snvs_1v8: LDO1 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1800000>;
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regulator-min-microvolt = <1800000>;
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regulator-name = "snvs-1v8";
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};
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ldo2_reg: LDO2 {
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regulator-always-on;
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regulator-max-microvolt = <1150000>;
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regulator-min-microvolt = <800000>;
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regulator-name = "LDO2";
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};
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reg_vdda_1v8: LDO3 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1800000>;
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regulator-min-microvolt = <1800000>;
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regulator-name = "vdda-1v8";
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};
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ldo4_reg: LDO4 {
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <800000>;
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regulator-name = "LDO4";
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};
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ldo5_reg: LDO5 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <1800000>;
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regulator-name = "LDO5";
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};
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};
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};
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};
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&iomuxc {
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pinctrl_eqos: eqosgrp {
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fsl,pins = <
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MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK
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(MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE | MX8MP_SION)
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MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC
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(MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
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MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO
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(MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
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MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0
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(MX8MP_DSE_X6 | MX8MP_FSEL_FAST)
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MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1
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(MX8MP_DSE_X6 | MX8MP_FSEL_FAST)
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MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0
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(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
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MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1
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(MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
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MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER
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(MX8MP_FSEL_FAST | MX8MP_PULL_ENABLE)
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MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL
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(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_ENABLE)
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MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL
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(MX8MP_DSE_X6 | MX8MP_FSEL_FAST)
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>;
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};
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pinctrl_eqos_sleep: eqos-sleep-grp {
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fsl,pins = <
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MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19
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(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
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MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16
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(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
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MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17
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(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
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MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21
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(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
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MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20
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(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
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MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26
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(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
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MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27
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(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
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MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25
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(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
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MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24
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(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
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MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22
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(MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE)
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>;
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};
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pinctrl_ethphy_int_b: ethphy-int-bgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21
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(MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT)
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>;
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};
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pinctrl_ethphy_rst_b: ethphy-rst-bgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22
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(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL
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MX8MP_I2C_DEFAULT
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MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA
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MX8MP_I2C_DEFAULT
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>;
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};
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pinctrl_i2c1_gpio: i2c1-gpiogrp {
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fsl,pins = <
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MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14
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MX8MP_I2C_DEFAULT
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MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15
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MX8MP_I2C_DEFAULT
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>;
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};
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pinctrl_pmic: pmicgrp {
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fsl,pins = <
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MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03
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(MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
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>;
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};
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pinctrl_reg_3v3_etn: reg-3v3-etngrp {
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fsl,pins = <
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MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23
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(MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
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(MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
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MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
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MX8MP_USDHC_DATA_DEFAULT
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MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
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MX8MP_USDHC_DATA_DEFAULT
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MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
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MX8MP_USDHC_DATA_DEFAULT
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MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
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MX8MP_USDHC_DATA_DEFAULT
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MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
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MX8MP_USDHC_DATA_DEFAULT
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MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4
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MX8MP_USDHC_DATA_DEFAULT
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MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5
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MX8MP_USDHC_DATA_DEFAULT
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MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6
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MX8MP_USDHC_DATA_DEFAULT
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MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7
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MX8MP_USDHC_DATA_DEFAULT
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
|
|
(MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
|
|
(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
|
|
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
|
|
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
|
|
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
|
|
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
|
|
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4
|
|
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5
|
|
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6
|
|
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7
|
|
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
|
|
(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
|
|
(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
|
|
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
|
|
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
|
|
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
|
|
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
|
|
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4
|
|
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5
|
|
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6
|
|
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7
|
|
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
|
|
(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
|
|
>;
|
|
};
|
|
};
|
|
|
|
&usdhc3 {
|
|
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
|
|
assigned-clock-rates = <200000000>;
|
|
bus-width = <8>;
|
|
max-frequency = <200000000>;
|
|
non-removable;
|
|
pinctrl-0 = <&pinctrl_usdhc3>;
|
|
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
|
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
vmmc-supply = <®_vdd_3v3>;
|
|
voltage-ranges = <3300 3300>;
|
|
vqmmc-supply = <®_nvcc_nand>;
|
|
status = "okay";
|
|
};
|