mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-11-01 09:13:37 +00:00
25501d8d3a
In the new behavior, the sja1105 driver expects there to be explicit
RGMII delays present on the fixed-link ports, otherwise it will complain
that it falls back to legacy behavior, which is to apply RGMII delays
incorrectly derived from the phy-mode string.
In this case, the legacy behavior of the driver is to apply both RX and
TX delays. To preserve that, add explicit 2 nanosecond delays, which are
identical with what the driver used to add (a 90 degree phase shift).
The delays from the phy-mode are ignored by new kernels (it's still
RGMII as long as it's "rgmii*" something), and the explicit
{rx,tx}-internal-delay-ps properties are ignored by old kernels, so the
change works both ways.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
662 lines
11 KiB
Text
662 lines
11 KiB
Text
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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//
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// Device Tree file for LX2160A BLUEBOX3
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//
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// Copyright 2020-2021 NXP
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/dts-v1/;
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#include "fsl-lx2160a.dtsi"
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/ {
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model = "NXP Layerscape LX2160ABLUEBOX3";
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compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a";
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aliases {
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crypto = &crypto;
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mmc0 = &esdhc0;
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mmc1 = &esdhc1;
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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sb_3v3: regulator-sb3v3 {
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compatible = "regulator-fixed";
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regulator-name = "MC34717-3.3VSB";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&can0 {
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status = "okay";
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can-transceiver {
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max-bitrate = <5000000>;
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};
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};
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&can1 {
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status = "okay";
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can-transceiver {
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max-bitrate = <5000000>;
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};
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};
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&crypto {
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status = "okay";
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};
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&dpmac5 {
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phy-handle = <&aqr113c_phy1>;
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phy-mode = "usxgmii";
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managed = "in-band-status";
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};
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&dpmac6 {
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phy-handle = <&aqr113c_phy2>;
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phy-mode = "usxgmii";
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managed = "in-band-status";
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};
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&dpmac9 {
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phy-handle = <&aqr113c_phy3>;
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phy-mode = "usxgmii";
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managed = "in-band-status";
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};
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&dpmac10 {
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phy-handle = <&aqr113c_phy4>;
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phy-mode = "usxgmii";
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managed = "in-band-status";
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};
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&dpmac17 {
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phy-mode = "rgmii";
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status = "okay";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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&dpmac18 {
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phy-mode = "rgmii";
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status = "okay";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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&emdio1 {
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status = "okay";
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aqr113c_phy2: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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/* IRQ_10G_PHY2 */
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interrupts-extended = <&extirq 3 IRQ_TYPE_LEVEL_LOW>;
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};
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aqr113c_phy1: ethernet-phy@8 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x8>;
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/* IRQ_10G_PHY1 */
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interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
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};
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sw1_mii3_phy: ethernet-phy@5 {
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/* AR8035 */
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compatible = "ethernet-phy-id004d.d072";
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reg = <0x5>;
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interrupts-extended = <&extirq 6 IRQ_TYPE_LEVEL_LOW>;
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};
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sw2_mii3_phy: ethernet-phy@6 {
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/* AR8035 */
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compatible = "ethernet-phy-id004d.d072";
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reg = <0x6>;
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interrupts-extended = <&extirq 7 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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&emdio2 {
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status = "okay";
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aqr113c_phy4: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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/* IRQ_10G_PHY4 */
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interrupts-extended = <&extirq 5 IRQ_TYPE_LEVEL_LOW>;
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};
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aqr113c_phy3: ethernet-phy@8 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x8>;
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/* IRQ_10G_PHY3 */
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interrupts-extended = <&extirq 4 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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&esdhc0 {
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sd-uhs-sdr104;
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sd-uhs-sdr50;
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sd-uhs-sdr25;
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sd-uhs-sdr12;
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status = "okay";
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};
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&esdhc1 {
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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bus-width = <8>;
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status = "okay";
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};
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&fspi {
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status = "okay";
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mt35xu512aba0: flash@0 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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m25p,fast-read;
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spi-max-frequency = <50000000>;
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spi-rx-bus-width = <8>;
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spi-tx-bus-width = <8>;
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};
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mt35xu512aba1: flash@1 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <1>;
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m25p,fast-read;
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spi-max-frequency = <50000000>;
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spi-rx-bus-width = <8>;
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spi-tx-bus-width = <8>;
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};
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};
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&i2c0 {
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status = "okay";
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i2c-mux@77 {
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compatible = "nxp,pca9547";
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reg = <0x77>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2>;
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power-monitor@40 {
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compatible = "ti,ina220";
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reg = <0x40>;
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shunt-resistor = <500>;
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};
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3>;
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temp2: temperature-sensor@48 {
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compatible = "nxp,sa56004";
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reg = <0x48>;
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vcc-supply = <&sb_3v3>;
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#thermal-sensor-cells = <1>;
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};
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temp1: temperature-sensor@4c {
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compatible = "nxp,sa56004";
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reg = <0x4c>;
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vcc-supply = <&sb_3v3>;
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#thermal-sensor-cells = <1>;
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};
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};
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i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x4>;
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rtc@51 {
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compatible = "nxp,pcf2129";
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reg = <0x51>;
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interrupts-extended = <&extirq 11 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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i2c@7 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x7>;
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i2c-mux@75 {
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compatible = "nxp,pca9547";
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reg = <0x75>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0>;
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spi_bridge: spi@28 {
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compatible = "nxp,sc18is602b";
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reg = <0x28>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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};
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};
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};
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&i2c5 {
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status = "okay";
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i2c-mux@77 {
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compatible = "nxp,pca9846";
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reg = <0x77>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x1>;
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/* The I2C multiplexer and temperature sensors are on
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* the T6 riser card.
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*/
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i2c-mux@70 {
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compatible = "nxp,pca9548";
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reg = <0x70>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@6 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x6>;
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q12: temperature-sensor@4c {
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compatible = "nxp,sa56004";
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reg = <0x4c>;
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vcc-supply = <&sb_3v3>;
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#thermal-sensor-cells = <1>;
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};
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};
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i2c@7 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x7>;
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q11: temperature-sensor@4c {
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compatible = "nxp,sa56004";
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reg = <0x4c>;
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vcc-supply = <&sb_3v3>;
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#thermal-sensor-cells = <1>;
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};
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q13: temperature-sensor@48 {
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compatible = "nxp,sa56004";
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reg = <0x48>;
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vcc-supply = <&sb_3v3>;
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#thermal-sensor-cells = <1>;
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};
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q14: temperature-sensor@4a {
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compatible = "nxp,sa56004";
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reg = <0x4a>;
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vcc-supply = <&sb_3v3>;
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#thermal-sensor-cells = <1>;
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};
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};
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};
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};
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};
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};
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&pcs_mdio5 {
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status = "okay";
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};
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&pcs_mdio6 {
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status = "okay";
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};
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&pcs_mdio9 {
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status = "okay";
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};
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&pcs_mdio10 {
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status = "okay";
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};
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&spi_bridge {
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sw1: ethernet-switch@0 {
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compatible = "nxp,sja1110a";
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reg = <0>;
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spi-max-frequency = <4000000>;
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spi-cpol;
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dsa,member = <0 0>;
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* Microcontroller port */
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port@0 {
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reg = <0>;
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status = "disabled";
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};
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/* SW1_P1 */
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port@1 {
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reg = <1>;
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label = "con_2x20";
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phy-mode = "sgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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port@2 {
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reg = <2>;
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ethernet = <&dpmac17>;
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phy-mode = "rgmii-id";
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rx-internal-delay-ps = <2000>;
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tx-internal-delay-ps = <2000>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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port@3 {
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reg = <3>;
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label = "1ge_p1";
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phy-mode = "rgmii-id";
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phy-handle = <&sw1_mii3_phy>;
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};
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sw1p4: port@4 {
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reg = <4>;
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link = <&sw2p1>;
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phy-mode = "sgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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port@5 {
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reg = <5>;
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label = "trx1";
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phy-mode = "internal";
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phy-handle = <&sw1_port5_base_t1_phy>;
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};
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port@6 {
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reg = <6>;
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label = "trx2";
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phy-mode = "internal";
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phy-handle = <&sw1_port6_base_t1_phy>;
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};
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port@7 {
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reg = <7>;
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label = "trx3";
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phy-mode = "internal";
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phy-handle = <&sw1_port7_base_t1_phy>;
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};
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port@8 {
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reg = <8>;
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label = "trx4";
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phy-mode = "internal";
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phy-handle = <&sw1_port8_base_t1_phy>;
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};
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port@9 {
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reg = <9>;
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label = "trx5";
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phy-mode = "internal";
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phy-handle = <&sw1_port9_base_t1_phy>;
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};
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port@a {
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reg = <10>;
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label = "trx6";
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phy-mode = "internal";
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phy-handle = <&sw1_port10_base_t1_phy>;
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};
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};
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mdios {
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#address-cells = <1>;
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#size-cells = <0>;
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mdio@0 {
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compatible = "nxp,sja1110-base-t1-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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sw1_port5_base_t1_phy: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x1>;
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};
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sw1_port6_base_t1_phy: ethernet-phy@2 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x2>;
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};
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sw1_port7_base_t1_phy: ethernet-phy@3 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x3>;
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};
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sw1_port8_base_t1_phy: ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x4>;
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};
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sw1_port9_base_t1_phy: ethernet-phy@5 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x5>;
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};
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sw1_port10_base_t1_phy: ethernet-phy@6 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x6>;
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};
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};
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};
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};
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sw2: ethernet-switch@2 {
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compatible = "nxp,sja1110a";
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reg = <2>;
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spi-max-frequency = <4000000>;
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spi-cpol;
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dsa,member = <0 1>;
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* Microcontroller port */
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port@0 {
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reg = <0>;
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status = "disabled";
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};
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sw2p1: port@1 {
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reg = <1>;
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link = <&sw1p4>;
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phy-mode = "sgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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port@2 {
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reg = <2>;
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ethernet = <&dpmac18>;
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phy-mode = "rgmii-id";
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rx-internal-delay-ps = <2000>;
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tx-internal-delay-ps = <2000>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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port@3 {
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reg = <3>;
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label = "1ge_p2";
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phy-mode = "rgmii-id";
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phy-handle = <&sw2_mii3_phy>;
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};
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port@4 {
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reg = <4>;
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label = "to_sw3";
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phy-mode = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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};
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};
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port@5 {
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reg = <5>;
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label = "trx7";
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phy-mode = "internal";
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phy-handle = <&sw2_port5_base_t1_phy>;
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};
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port@6 {
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reg = <6>;
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label = "trx8";
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phy-mode = "internal";
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phy-handle = <&sw2_port6_base_t1_phy>;
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};
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port@7 {
|
|
reg = <7>;
|
|
label = "trx9";
|
|
phy-mode = "internal";
|
|
phy-handle = <&sw2_port7_base_t1_phy>;
|
|
};
|
|
|
|
port@8 {
|
|
reg = <8>;
|
|
label = "trx10";
|
|
phy-mode = "internal";
|
|
phy-handle = <&sw2_port8_base_t1_phy>;
|
|
};
|
|
|
|
port@9 {
|
|
reg = <9>;
|
|
label = "trx11";
|
|
phy-mode = "internal";
|
|
phy-handle = <&sw2_port9_base_t1_phy>;
|
|
};
|
|
|
|
port@a {
|
|
reg = <10>;
|
|
label = "trx12";
|
|
phy-mode = "internal";
|
|
phy-handle = <&sw2_port10_base_t1_phy>;
|
|
};
|
|
};
|
|
|
|
mdios {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
mdio@0 {
|
|
compatible = "nxp,sja1110-base-t1-mdio";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0>;
|
|
|
|
sw2_port5_base_t1_phy: ethernet-phy@1 {
|
|
compatible = "ethernet-phy-ieee802.3-c45";
|
|
reg = <0x1>;
|
|
};
|
|
|
|
sw2_port6_base_t1_phy: ethernet-phy@2 {
|
|
compatible = "ethernet-phy-ieee802.3-c45";
|
|
reg = <0x2>;
|
|
};
|
|
|
|
sw2_port7_base_t1_phy: ethernet-phy@3 {
|
|
compatible = "ethernet-phy-ieee802.3-c45";
|
|
reg = <0x3>;
|
|
};
|
|
|
|
sw2_port8_base_t1_phy: ethernet-phy@4 {
|
|
compatible = "ethernet-phy-ieee802.3-c45";
|
|
reg = <0x4>;
|
|
};
|
|
|
|
sw2_port9_base_t1_phy: ethernet-phy@5 {
|
|
compatible = "ethernet-phy-ieee802.3-c45";
|
|
reg = <0x5>;
|
|
};
|
|
|
|
sw2_port10_base_t1_phy: ethernet-phy@6 {
|
|
compatible = "ethernet-phy-ieee802.3-c45";
|
|
reg = <0x6>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&uart0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&uart1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb1 {
|
|
status = "okay";
|
|
};
|