mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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3aefb2ee5b
This series is based on the alternatives changes done in my svpbmt series and thus also depends on Atish's isa-extension parsing series. It implements using the cache-management instructions from the Zicbom- extension to handle cache flush, etc actions on platforms needing them. SoCs using cpu cores from T-Head like the Allwinne D1 implement a different set of cache instructions. But while they are different, instructions they provide the same functionality, so a variant can easly hook into the existing alternatives mechanism on those. [Palmer: Some minor fixups, including a RISCV_ISA_ZICBOM dependency on MMU that's probably not strictly necessary. The Zicbom support will trip up sparse for users that have new toolchains, I just sent a patch.] Link: https://lore.kernel.org/all/20220706231536.2041855-1-heiko@sntech.de/ Link: https://lore.kernel.org/linux-sparse/20220811033138.20676-1-palmer@rivosinc.com/T/#u * palmer/riscv-zicbom: riscv: implement cache-management errata for T-Head SoCs riscv: Add support for non-coherent devices using zicbom extension dt-bindings: riscv: document cbom-block-size of: also handle dma-noncoherent in of_dma_is_coherent()
166 lines
4.8 KiB
Makefile
166 lines
4.8 KiB
Makefile
# This file is included by the global makefile so that you can add your own
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# architecture-specific flags and dependencies.
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#
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# This file is subject to the terms and conditions of the GNU General Public
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# License. See the file "COPYING" in the main directory of this archive
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# for more details.
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#
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OBJCOPYFLAGS := -O binary
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LDFLAGS_vmlinux :=
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ifeq ($(CONFIG_DYNAMIC_FTRACE),y)
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LDFLAGS_vmlinux := --no-relax
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KBUILD_CPPFLAGS += -DCC_USING_PATCHABLE_FUNCTION_ENTRY
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CC_FLAGS_FTRACE := -fpatchable-function-entry=8
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endif
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ifeq ($(CONFIG_CMODEL_MEDLOW),y)
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KBUILD_CFLAGS_MODULE += -mcmodel=medany
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endif
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export BITS
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ifeq ($(CONFIG_ARCH_RV64I),y)
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BITS := 64
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UTS_MACHINE := riscv64
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KBUILD_CFLAGS += -mabi=lp64
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KBUILD_AFLAGS += -mabi=lp64
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KBUILD_LDFLAGS += -melf64lriscv
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else
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BITS := 32
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UTS_MACHINE := riscv32
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KBUILD_CFLAGS += -mabi=ilp32
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KBUILD_AFLAGS += -mabi=ilp32
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KBUILD_LDFLAGS += -melf32lriscv
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endif
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ifeq ($(CONFIG_LD_IS_LLD),y)
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KBUILD_CFLAGS += -mno-relax
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KBUILD_AFLAGS += -mno-relax
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ifndef CONFIG_AS_IS_LLVM
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KBUILD_CFLAGS += -Wa,-mno-relax
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KBUILD_AFLAGS += -Wa,-mno-relax
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endif
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endif
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# ISA string setting
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riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
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riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima
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riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
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riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
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# Newer binutils versions default to ISA spec version 20191213 which moves some
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# instructions from the I extension to the Zicsr and Zifencei extensions.
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toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei)
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riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei
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# Check if the toolchain supports Zicbom extension
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toolchain-supports-zicbom := $(call cc-option-yn, -march=$(riscv-march-y)_zicbom)
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riscv-march-$(toolchain-supports-zicbom) := $(riscv-march-y)_zicbom
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KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))
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KBUILD_AFLAGS += -march=$(riscv-march-y)
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KBUILD_CFLAGS += -mno-save-restore
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KBUILD_CFLAGS += -DCONFIG_PAGE_OFFSET=$(CONFIG_PAGE_OFFSET)
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ifeq ($(CONFIG_CMODEL_MEDLOW),y)
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KBUILD_CFLAGS += -mcmodel=medlow
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endif
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ifeq ($(CONFIG_CMODEL_MEDANY),y)
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KBUILD_CFLAGS += -mcmodel=medany
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endif
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ifeq ($(CONFIG_PERF_EVENTS),y)
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KBUILD_CFLAGS += -fno-omit-frame-pointer
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endif
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KBUILD_CFLAGS_MODULE += $(call cc-option,-mno-relax)
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KBUILD_AFLAGS_MODULE += $(call as-option,-Wa$(comma)-mno-relax)
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# GCC versions that support the "-mstrict-align" option default to allowing
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# unaligned accesses. While unaligned accesses are explicitly allowed in the
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# RISC-V ISA, they're emulated by machine mode traps on all extant
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# architectures. It's faster to have GCC emit only aligned accesses.
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KBUILD_CFLAGS += $(call cc-option,-mstrict-align)
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ifeq ($(CONFIG_STACKPROTECTOR_PER_TASK),y)
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prepare: stack_protector_prepare
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stack_protector_prepare: prepare0
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$(eval KBUILD_CFLAGS += -mstack-protector-guard=tls \
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-mstack-protector-guard-reg=tp \
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-mstack-protector-guard-offset=$(shell \
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awk '{if ($$2 == "TSK_STACK_CANARY") print $$3;}' \
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include/generated/asm-offsets.h))
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endif
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# arch specific predefines for sparse
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CHECKFLAGS += -D__riscv -D__riscv_xlen=$(BITS)
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# Default target when executing plain make
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boot := arch/riscv/boot
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ifeq ($(CONFIG_XIP_KERNEL),y)
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KBUILD_IMAGE := $(boot)/xipImage
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else
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KBUILD_IMAGE := $(boot)/Image.gz
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endif
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head-y := arch/riscv/kernel/head.o
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libs-y += arch/riscv/lib/
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libs-$(CONFIG_EFI_STUB) += $(objtree)/drivers/firmware/efi/libstub/lib.a
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PHONY += vdso_install
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vdso_install:
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$(Q)$(MAKE) $(build)=arch/riscv/kernel/vdso $@
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$(if $(CONFIG_COMPAT),$(Q)$(MAKE) \
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$(build)=arch/riscv/kernel/compat_vdso compat_$@)
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ifeq ($(KBUILD_EXTMOD),)
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ifeq ($(CONFIG_MMU),y)
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prepare: vdso_prepare
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vdso_prepare: prepare0
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$(Q)$(MAKE) $(build)=arch/riscv/kernel/vdso include/generated/vdso-offsets.h
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$(if $(CONFIG_COMPAT),$(Q)$(MAKE) \
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$(build)=arch/riscv/kernel/compat_vdso include/generated/compat_vdso-offsets.h)
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endif
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endif
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ifneq ($(CONFIG_XIP_KERNEL),y)
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ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_SOC_CANAAN),yy)
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KBUILD_IMAGE := $(boot)/loader.bin
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else
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KBUILD_IMAGE := $(boot)/Image.gz
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endif
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endif
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BOOT_TARGETS := Image Image.gz loader loader.bin xipImage
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all: $(notdir $(KBUILD_IMAGE))
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$(BOOT_TARGETS): vmlinux
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$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
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@$(kecho) ' Kernel: $(boot)/$@ is ready'
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Image.%: Image
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$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
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install: KBUILD_IMAGE := $(boot)/Image
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zinstall: KBUILD_IMAGE := $(boot)/Image.gz
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install zinstall:
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$(call cmd,install)
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PHONY += rv32_randconfig
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rv32_randconfig:
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$(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/riscv/configs/32-bit.config \
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-f $(srctree)/Makefile randconfig
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PHONY += rv64_randconfig
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rv64_randconfig:
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$(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/riscv/configs/64-bit.config \
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-f $(srctree)/Makefile randconfig
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PHONY += rv32_defconfig
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rv32_defconfig:
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$(Q)$(MAKE) -f $(srctree)/Makefile defconfig 32-bit.config
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