linux/Documentation/devicetree/bindings/cache
Varadarajan Narayanan f35a4397be dt-bindings: cache: qcom,llcc: Add IPQ5424 compatible
Document the Last Level Cache Controller on IPQ5424. The
'broadcast' register space is present only in chipsets that have
multiple instances of LLCC IP. Since IPQ5424 has only one
instance, both the LLCC and LLCC_BROADCAST points to the same
register space.

Hence, allow only '1' reg & reg-names entry for IPQ5424.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20241121051935.1055222-2-quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07 20:16:21 -06:00
..
andestech,ax45mp-cache.yaml dt-bindings: cache: andestech,ax45mp-cache: Fix unit address in example 2023-10-04 08:33:11 -05:00
baikal,bt1-l2-ctl.yaml
freescale-l2cache.txt
l2c2x0.yaml dt-bindings: Fix array property constraints 2024-10-01 21:17:00 -05:00
marvell,feroceon-cache.txt
marvell,tauros2-cache.txt
qcom,llcc.yaml dt-bindings: cache: qcom,llcc: Add IPQ5424 compatible 2025-01-07 20:16:21 -06:00
sifive,ccache0.yaml dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible 2023-11-22 11:58:08 +00:00
socionext,uniphier-system-cache.yaml
starfive,jh8100-starlink-cache.yaml dt-bindings: cache: Add docs for StarFive Starlink cache controller 2024-05-28 12:34:11 +01:00