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linux/drivers/gpu/drm/amd/include/asic_reg/dcn
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Bhawanpreet Lakha 9713158cb2 drm/amdgpu: Add and use seperate reg headers for dcn302 
Currently we are using dcn3 reg headers for dcn302. The offsets are
different between the two so they need seperate headers.

Add dcn302 header files and use these instead of dcn3 header

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-10 14:15:08 -05:00
..
dcn_1_0_offset.h
dcn_1_0_sh_mask.h
dcn_2_0_0_offset.h drm/amd/include: Add OCSC registers 2020-01-16 13:41:06 -05:00
dcn_2_0_0_sh_mask.h drm/amd/include: Add OCSC registers 2020-01-16 13:41:06 -05:00
dcn_2_1_0_offset.h drm/amd/include: Add OCSC registers 2020-01-16 13:41:06 -05:00
dcn_2_1_0_sh_mask.h drm/amd/include: Add OCSC registers 2020-01-16 13:41:06 -05:00
dcn_3_0_0_offset.h drm/amd/display: remove unintended executable mode 2020-08-24 12:23:02 -04:00
dcn_3_0_0_sh_mask.h drm/amd/display: remove unintended executable mode 2020-08-24 12:23:02 -04:00
dcn_3_0_1_offset.h drm/amdgpu: add vangogh asic header files (v2) 2020-10-05 15:14:02 -04:00
dcn_3_0_1_sh_mask.h drm/amdgpu: add vangogh asic header files (v2) 2020-10-05 15:14:02 -04:00
dcn_3_0_2_offset.h drm/amdgpu: Add and use seperate reg headers for dcn302 2020-11-10 14:15:08 -05:00
dcn_3_0_2_sh_mask.h drm/amdgpu: Add and use seperate reg headers for dcn302 2020-11-10 14:15:08 -05:00
dpcs_3_0_0_offset.h drm/amd/display: remove unintended executable mode 2020-08-24 12:23:02 -04:00
dpcs_3_0_0_sh_mask.h drm/amd/display: remove unintended executable mode 2020-08-24 12:23:02 -04:00