Alex Deucher 88d5cb2517 drm/amdgpu/display: drop DCN support for aarch64 ... From Ard: "Simply disabling -mgeneral-regs-only left and right is risky, given that the standard AArch64 ABI permits the use of FP/SIMD registers anywhere, and GCC is known to use SIMD registers for spilling, and may invent other uses of the FP/SIMD register file that have nothing to do with the floating point code in question. Note that putting kernel_neon_begin() and kernel_neon_end() around the code that does use FP is not sufficient here, the problem is in all the other code that may be emitted with references to SIMD registers in it. So the only way to do this properly is to put all floating point code in a separate compilation unit, and only compile that unit with -mgeneral-regs-only." Disable support until the code can be properly refactored to support this properly on aarch64. Acked-by: Will Deacon <will@kernel.org> Reported-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-01-05 11:35:53 -05:00
..
dcn20_dccg.c
dcn20_dccg.h	drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)	2020-11-04 17:11:37 -05:00
dcn20_dpp.c
dcn20_dpp.h	drm/amd/display: Add DSCL memory low power support	2020-12-01 16:03:40 -05:00
dcn20_dpp_cm.c
dcn20_dsc.c
dcn20_dsc.h
dcn20_dwb.c
dcn20_dwb.h
dcn20_dwb_scl.c
dcn20_hubbub.c	drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)	2020-11-04 17:11:37 -05:00
dcn20_hubbub.h
dcn20_hubp.c	drm/amd/display: Interfaces for hubp blank and soft reset	2020-12-23 15:01:24 -05:00
dcn20_hubp.h	drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)	2020-11-04 17:11:37 -05:00
dcn20_hwseq.c	drm/amd/display: Multi-display underflow observed	2020-12-23 15:02:18 -05:00
dcn20_hwseq.h
dcn20_init.c
dcn20_init.h
dcn20_link_encoder.c
dcn20_link_encoder.h	drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)	2020-11-04 17:11:37 -05:00
dcn20_mmhubbub.c
dcn20_mmhubbub.h
dcn20_mpc.c	drm/amd/display: add getter routine to retrieve mpcc mux	2020-12-23 15:02:55 -05:00
dcn20_mpc.h
dcn20_opp.c
dcn20_opp.h
dcn20_optc.c
dcn20_optc.h
dcn20_resource.c	drm/amd/display: Acquire DSC during split stream for ODM only if top_pipe	2020-12-23 15:02:24 -05:00
dcn20_resource.h	drm/amd/display: Prevent freesync power optimization during validation	2020-11-10 14:24:48 -05:00
dcn20_stream_encoder.c
dcn20_stream_encoder.h	drm/amd/display: Add missing DP_SEC register definitions and masks	2020-12-15 11:33:33 -05:00
dcn20_vmid.c
dcn20_vmid.h
Makefile	drm/amdgpu/display: drop DCN support for aarch64	2021-01-05 11:35:53 -05:00