linux/drivers/gpu/drm/amd/display/dc/clk_mgr
Alex Deucher 88d5cb2517 drm/amdgpu/display: drop DCN support for aarch64
From Ard:

"Simply disabling -mgeneral-regs-only left and right is risky, given that
the standard AArch64 ABI permits the use of FP/SIMD registers anywhere,
and GCC is known to use SIMD registers for spilling, and may invent
other uses of the FP/SIMD register file that have nothing to do with the
floating point code in question. Note that putting kernel_neon_begin()
and kernel_neon_end() around the code that does use FP is not sufficient
here, the problem is in all the other code that may be emitted with
references to SIMD registers in it.

So the only way to do this properly is to put all floating point code in
a separate compilation unit, and only compile that unit with
-mgeneral-regs-only."

Disable support until the code can be properly refactored to support this
properly on aarch64.

Acked-by: Will Deacon <will@kernel.org>
Reported-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-01-05 11:35:53 -05:00
..
dce60 drm/amd/display: dc/clk_mgr: make function static 2020-09-17 21:21:40 -04:00
dce100
dce110 drm/amd/display: correct asic type check V2 2020-10-27 12:01:16 -04:00
dce112 drm/amd/display: correct asic type check V2 2020-10-27 12:01:16 -04:00
dce120
dcn10 drm/amd/display: Tune min clk values for MPO for RV 2020-11-02 15:32:50 -05:00
dcn20
dcn21 drm/amd/display: always program DPPDTO unless not safe to lower 2020-12-23 15:02:47 -05:00
dcn30 drm/amd/display: Expose clk_mgr functions for reuse 2020-12-08 23:03:39 -05:00
dcn301 drm/amd/display: Update RN/VGH active display count workaround 2020-12-23 15:02:06 -05:00
clk_mgr.c drm/amd/display: Engage PSR synchronously 2020-11-10 14:24:55 -05:00
Makefile drm/amdgpu/display: drop DCN support for aarch64 2021-01-05 11:35:53 -05:00