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linux/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi
Linus Torvalds 2f24482304 soc: devicetree updates for 6.15 
There is new support for additional on-chip devices on Apple, Mediatek,
 Renesas, Rockchip, Samsung, Google, TI, ST, Nvidia and Amlogic devices.
 
 The Arm Morello reference platform gets a devicetree for booting in
 normal aarch64 mode. The hardware supports experimental CHERI support,
 which requires a modified kernel.
 
 The AMD (formerly Xilinx) Versal NET SoC gets added, this is a combined
 FPGA with Cortex-A78 CPUs in a SoC.
 
 Six new ST STM32MP2 SoC variants are added. Like the earlier STM32MP25,
 the MP211, MP213, MP215, MP231, MP233 and MP235 models are based on one
 or two Cortex-A35 cores but each feature a different set of I/O devices.
 
 Mediatek MT8370 is a minor variation of MT8390 with fewer CPU and
 GPU cores
 
 Apple T2 is the baseboard management controller on earlier Intel CPU
 based Macs, with 16 models now gaining initial support.
 
 All the above come with dts files for the reference boards. In
 addition, these boards are added for the SoCs that are already supported.
 
  - The Milk-V Jupiter board based on SpacemiT K1/M1
 
  - NetCube Systems Kumquat board based on the 32-bit Allwinner V3s SoC
 
  - Three boards based on 32-bit stm32mp1
 
  - 11 distinct board variants from Toradex and one from Variscite,
    all based on i.MX6
 
  - Google Pixel Pro 6 phone based on gs101 (Tensor)
 
  - Three additional variants of the i.MX8MP based "Skov" board
 
  - A second variant of the i.MX95 EVK board
 
  - Two boards based on Renesas SoCs
 
  - Four boards based the Rockchip RK35xx series, plus the RK3588
    "MNT Reform 2" laptop
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Merge tag 'soc-dt-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC devicetree updates from Arnd Bergmann:
 "There is new support for additional on-chip devices on Apple,
  Mediatek, Renesas, Rockchip, Samsung, Google, TI, ST, Nvidia and
  Amlogic devices.

  The Arm Morello reference platform gets a devicetree for booting in
  normal aarch64 mode. The hardware supports experimental CHERI support,
  which requires a modified kernel.

  The AMD (formerly Xilinx) Versal NET SoC gets added, this is a
  combined FPGA with Cortex-A78 CPUs in a SoC.

  Six new ST STM32MP2 SoC variants are added. Like the earlier
  STM32MP25, the MP211, MP213, MP215, MP231, MP233 and MP235 models are
  based on one or two Cortex-A35 cores but each feature a different set
  of I/O devices.

  Mediatek MT8370 is a minor variation of MT8390 with fewer CPU and GPU
  cores

  Apple T2 is the baseboard management controller on earlier Intel CPU
  based Macs, with 16 models now gaining initial support.

  All the above come with dts files for the reference boards. In
  addition, these boards are added for the SoCs that are already
  supported:

   - The Milk-V Jupiter board based on SpacemiT K1/M1

   - NetCube Systems Kumquat board based on the 32-bit Allwinner V3s SoC

   - Three boards based on 32-bit stm32mp1

   - 11 distinct board variants from Toradex and one from Variscite, all
     based on i.MX6

   - Google Pixel Pro 6 phone based on gs101 (Tensor)

   - Three additional variants of the i.MX8MP based "Skov" board

   - A second variant of the i.MX95 EVK board

   - Two boards based on Renesas SoCs

   - Four boards based the Rockchip RK35xx series, plus the RK3588 'MNT
     Reform 2' laptop"

* tag 'soc-dt-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (538 commits)
  arm64: dts: Add gpio_intc node for Amlogic A5 SoCs
  arm64: dts: Add gpio_intc node for Amlogic A4 SoCs
  arm64: dts: hi3660: Add property for fixing CPUIdle
  arm64: dts: rockchip: remove ethm0_clk0_25m_out from Sige5 gmac0
  arm64: dts: marvell: Use preferred node names for "simple-bus"
  arm64: dts: marvell: Drop unused CP11X_TYPE define
  arm64: dts: marvell: Move arch timer and pmu nodes to top-level
  arm64: dts: rockchip: Fix PWM pinctrl names
  arm64: dts: rockchip: fix RK3576 SCMI clock IDs
  dt-bindings: clock: rk3576: add SCMI clocks
  arm64: dts: rockchip: Fix pcie reset gpio on Orange Pi 5 Max
  arm64: dts: amd/seattle: Drop undocumented "spi-controller" properties
  arm64: dts: amd/seattle: Fix bus, mmc, and ethernet node names
  arm64: dts: amd/seattle: Move and simplify fixed clocks
  arm64: dts: amd/seattle: Base Overdrive B1 on top of B0 version
  arm64: dts: rockchip: Enable HDMI audio output for ArmSoM Sige7
  arm64: dts: rockchip: Enable onboard eMMC on Radxa E20C
  arm64: dts: rockchip: Add SDHCI controller for RK3528
  arm64: dts: rockchip: Remove bluetooth node from rock-3a
  arm64: dts: rockchip: Move rk356x scmi SHMEM to reserved memory
  ...
2025-03-27 09:01:37 -07:00

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
#include "imx8mp.dtsi"
#include "imx8mp-nominal.dtsi"
#include <dt-bindings/leds/common.h>
/ {
aliases {
/* some of this aliases like backlight0, ethernetX and switch0
* are needed for the bootloader.
*/
backlight0 = &backlight;
ethernet0 = &eqos;
ethernet1 = &lan1;
ethernet2 = &lan2;
rtc0 = &i2c_rtc;
rtc1 = &snvs_rtc;
switch0 = &switch;
};
/*
* Backlight is present only on some of boards, so it is disabled by
* default.
*/
backlight: backlight {
compatible = "pwm-backlight";
pinctrl-0 = <&pinctrl_backlight>;
pwms = <&pwm1 0 20000 0>;
power-supply = <&reg_24v>;
enable-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
brightness-levels = <0 255>;
num-interpolated-steps = <17>;
default-brightness-level = <8>;
status = "disabled";
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
led-0 {
label = "D1";
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_STATUS;
default-state = "on";
linux,default-trigger = "heartbeat";
};
led-1 {
label = "D2";
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-2 {
label = "D3";
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
reg_1v2: regulator-1v2 {
compatible = "regulator-fixed";
vin-supply = <&reg_5v_p>;
regulator-name = "1V2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
reg_2v5: regulator-2v5 {
compatible = "regulator-fixed";
vin-supply = <&reg_5v_s>;
regulator-name = "2V5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
vin-supply = <&reg_5v_s>;
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
/*
* This regulator will provide power as long as possible even if
* undervoltage is detected.
*/
reg_5v_p: regulator-5v-p {
compatible = "regulator-fixed";
regulator-name = "5V_P";
vin-supply = <&reg_24v>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
/*
* This regulator will be automatically shutdown if undervoltage is
* detected.
*/
reg_5v_s: regulator-5v-s {
compatible = "regulator-fixed";
regulator-name = "5V_S";
vin-supply = <&reg_24v>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_24v: regulator-24v {
compatible = "regulator-fixed";
regulator-name = "24V";
regulator-min-microvolt = <24000000>;
regulator-max-microvolt = <24000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg24v>;
interrupts-extended = <&gpio4 23 IRQ_TYPE_EDGE_FALLING>;
system-critical-regulator;
regulator-uv-less-critical-window-ms = <50>;
};
reg_can2rs: regulator-can2rs {
compatible = "regulator-fixed";
regulator-name = "CAN2RS";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can2rs>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 22 GPIO_ACTIVE_LOW>;
};
reg_canrs: regulator-canrs {
compatible = "regulator-fixed";
regulator-name = "CANRS";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_canrs>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
};
reg_tft_vcom: regulator-tft-vcom {
compatible = "pwm-regulator";
pwms = <&pwm4 0 20000 0>;
regulator-name = "VCOM";
vin-supply = <&reg_5v_s>;
regulator-min-microvolt = <3600000>;
regulator-max-microvolt = <3600000>;
regulator-always-on;
voltage-table = <3600000 26>;
status = "disabled";
};
reg_vsd_3v3: regulator-vsd-3v3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_vsd_3v3>;
vin-supply = <&reg_vdd_3v3>;
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
/*
* Board is passively cooled and heatsink is specced for continuous operation
* at 1.2 GHz only. Short bouts of 1.6 GHz are ok, but these should be done
* intentionally, not as part of suspend/resume cycles.
*/
&{/opp-table/opp-1600000000} {
/delete-property/ opp-suspend;
};
&{/opp-table/opp-1800000000} {
/delete-property/ opp-suspend;
};
&A53_0 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_1 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_2 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_3 {
cpu-supply = <&reg_vdd_arm>;
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
adc: adc@0 {
compatible = "microchip,mcp3002";
reg = <0>;
vref-supply = <&reg_vdd_3v3>;
spi-max-frequency = <1000000>;
#io-channel-cells = <1>;
};
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-rxid";
status = "okay";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_canrs>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_can2rs>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupts-extended = <&gpio1 3 IRQ_TYPE_EDGE_RISING>;
regulators {
reg_vdd_soc: BUCK1 {
regulator-name = "VDD_SOC";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
vin-supply = <&reg_5v_p>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
reg_vdd_arm: BUCK2 {
regulator-name = "VDD_ARM";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1000000>;
vin-supply = <&reg_5v_p>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <850000>;
nxp,dvs-standby-voltage = <850000>;
};
reg_vdd_3v3: BUCK4 {
regulator-name = "VDD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&reg_5v_p>;
regulator-boot-on;
regulator-always-on;
};
reg_vdd_1v8: BUCK5 {
regulator-name = "VDD_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&reg_5v_p>;
regulator-boot-on;
regulator-always-on;
};
reg_nvcc_dram_1v1: BUCK6 {
regulator-name = "NVCC_DRAM_1V1";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
vin-supply = <&reg_5v_p>;
regulator-boot-on;
regulator-always-on;
};
reg_nvcc_snvs_1v8: LDO1 {
regulator-name = "NVCC_SNVS_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&reg_5v_p>;
regulator-boot-on;
regulator-always-on;
};
reg_vdda_1v8: LDO3 {
regulator-name = "VDDA_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&reg_5v_p>;
regulator-boot-on;
regulator-always-on;
};
reg_nvcc_sd2: LDO5 {
regulator-name = "NVCC_SD2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&reg_5v_p>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c2 {
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
i2c_rtc: rtc@51 {
compatible = "nxp,pcf85063tp";
reg = <0x51>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
interrupts-extended = <&gpio4 31 IRQ_TYPE_EDGE_FALLING>;
quartz-load-femtofarads = <12500>;
};
};
&i2c4 {
clock-frequency = <380000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
switch: switch@5f {
compatible = "microchip,ksz9893";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_switch>;
reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
reg = <0x5f>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
lan1: port@0 {
reg = <0>;
phy-mode = "internal";
label = "lan1";
};
lan2: port@1 {
reg = <1>;
phy-mode = "internal";
label = "lan2";
};
port@2 {
reg = <2>;
label = "cpu";
ethernet = <&eqos>;
phy-mode = "rgmii";
/* 2ns RX delay is implemented on PCB */
tx-internal-delay-ps = <2000>;
rx-internal-delay-ps = <0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
/*
* While there is no CTS line, the property "uart-has-rtscts" is still
* the right thing to do to enable the UART to do RS485. In RS485-Mode
* CTS isn't used anyhow and there is no dedicated property
* "uart-has-rts-but-no-cts".
*/
uart-has-rtscts;
};
&uart2 {
/* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb3_phy0 {
vbus-supply = <&reg_3v3>;
status = "okay";
};
&usb3_phy1 {
vbus-supply = <&reg_3v3>;
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "host";
};
&usb_dwc3_1 {
dr_mode = "host";
};
/* SD Card */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
vmmc-supply = <&reg_vsd_3v3>;
vqmmc-supply = <&reg_nvcc_sd2>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
status = "okay";
};
/* eMMC */
&usdhc3 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
vmmc-supply = <&reg_vdd_3v3>;
vqmmc-supply = <&reg_vdd_1v8>;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_backlight: backlightgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x0100
>;
};
pinctrl_can2rs: can2rsgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x154
>;
};
pinctrl_canrs: canrsgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x154
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40
>;
};
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154
MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x19
MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x19
MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c2
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c2
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2
MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
>;
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3
MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x116
>;
};
pinctrl_reg24v: reg24vgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x154
>;
};
pinctrl_reg_vsd_3v3: regvsd3v3grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x41
>;
};
pinctrl_switch: switchgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x41
MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x41
>;
};
pinctrl_touchscreen: touchscreengrp {
fsl,pins = <
/* external 10 k pull up */
/* CTP_INT */
MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x41
/* CTP_RST */
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x41
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
MX8MP_IOMUXC_UART3_RXD__UART1_DTE_RTS 0x140
/* CTS pin is not connected, but needed as workaround */
MX8MP_IOMUXC_UART3_TXD__UART1_DTE_CTS 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x1c4
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
>;
};
};
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