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25422e8f46
RSCI of RZ/T2H SoC (a.k.a r9a09g077), as a lot of similarities with SCI in other Renesas SoC like G2L, G3S, V2L; However, it has a different set of registers, and in addition to serial, this IP also supports SCIe (encoder), SmartCard, i2c and spi. This is why the 'renesas,sci' fallback for generic SCI does not apply for it. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com> Link: https://lore.kernel.org/r/20250403212919.1137670-4-thierry.bultel.yh@bp.renesas.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
78 lines
1.7 KiB
YAML
78 lines
1.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/serial/renesas,rsci.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RSCI Serial Communication Interface
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maintainers:
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- Geert Uytterhoeven <geert+renesas@glider.be>
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- Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
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allOf:
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- $ref: serial.yaml#
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properties:
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compatible:
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const: renesas,r9a09g077-rsci # RZ/T2H
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reg:
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maxItems: 1
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interrupts:
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items:
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- description: Error interrupt
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- description: Receive buffer full interrupt
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- description: Transmit buffer empty interrupt
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- description: Transmit end interrupt
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interrupt-names:
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items:
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- const: eri
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- const: rxi
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- const: txi
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- const: tei
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clocks:
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maxItems: 1
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clock-names:
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const: fck # UART functional clock
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power-domains:
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maxItems: 1
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uart-has-rtscts: false
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- power-domains
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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aliases {
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serial0 = &sci0;
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};
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sci0: serial@80005000 {
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compatible = "renesas,r9a09g077-rsci";
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reg = <0x80005000 0x400>;
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interrupts = <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 591 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 592 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "eri", "rxi", "txi", "tei";
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clocks = <&cpg CPG_MOD 108>;
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clock-names = "fck";
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power-domains = <&cpg>;
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};
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