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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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37443ef3f0
This paves the way for allowing individual CPUs to overload the individual flushing routines that they care about without having to depend on weak aliases. SH-4 is converted over initially, as it wires up pretty much everything. The majority of the other CPUs will simply use the default no-op implementation with their own region flushers wired up. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
135 lines
3.3 KiB
C
135 lines
3.3 KiB
C
#include <linux/mm.h>
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#include <asm/mmu_context.h>
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#include <asm/cacheflush.h>
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/*
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* Write back the dirty D-caches, but not invalidate them.
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*
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* START: Virtual Address (U0, P1, or P3)
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* SIZE: Size of the region.
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*/
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static void sh4__flush_wback_region(void *start, int size)
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{
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reg_size_t aligned_start, v, cnt, end;
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aligned_start = register_align(start);
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v = aligned_start & ~(L1_CACHE_BYTES-1);
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end = (aligned_start + size + L1_CACHE_BYTES-1)
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& ~(L1_CACHE_BYTES-1);
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cnt = (end - v) / L1_CACHE_BYTES;
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while (cnt >= 8) {
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asm volatile("ocbwb @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbwb @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbwb @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbwb @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbwb @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbwb @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbwb @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbwb @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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cnt -= 8;
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}
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while (cnt) {
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asm volatile("ocbwb @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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cnt--;
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}
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}
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/*
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* Write back the dirty D-caches and invalidate them.
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*
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* START: Virtual Address (U0, P1, or P3)
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* SIZE: Size of the region.
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*/
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static void sh4__flush_purge_region(void *start, int size)
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{
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reg_size_t aligned_start, v, cnt, end;
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aligned_start = register_align(start);
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v = aligned_start & ~(L1_CACHE_BYTES-1);
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end = (aligned_start + size + L1_CACHE_BYTES-1)
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& ~(L1_CACHE_BYTES-1);
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cnt = (end - v) / L1_CACHE_BYTES;
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while (cnt >= 8) {
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asm volatile("ocbp @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbp @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbp @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbp @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbp @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbp @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbp @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbp @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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cnt -= 8;
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}
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while (cnt) {
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asm volatile("ocbp @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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cnt--;
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}
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}
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/*
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* No write back please
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*/
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static void sh4__flush_invalidate_region(void *start, int size)
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{
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reg_size_t aligned_start, v, cnt, end;
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aligned_start = register_align(start);
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v = aligned_start & ~(L1_CACHE_BYTES-1);
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end = (aligned_start + size + L1_CACHE_BYTES-1)
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& ~(L1_CACHE_BYTES-1);
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cnt = (end - v) / L1_CACHE_BYTES;
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while (cnt >= 8) {
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asm volatile("ocbi @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbi @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbi @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbi @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbi @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbi @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbi @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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asm volatile("ocbi @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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cnt -= 8;
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}
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while (cnt) {
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asm volatile("ocbi @%0" : : "r" (v));
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v += L1_CACHE_BYTES;
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cnt--;
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}
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}
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void __init sh4__flush_region_init(void)
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{
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__flush_wback_region = sh4__flush_wback_region;
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__flush_invalidate_region = sh4__flush_invalidate_region;
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__flush_purge_region = sh4__flush_purge_region;
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}
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