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36f257e3b0
When PCIe AER is in FW-First, OS should process CXL Protocol errors from CPER records. Introduce support for handling and logging CXL Protocol errors. The defined trace events cxl_aer_uncorrectable_error and cxl_aer_correctable_error trace native CXL AER endpoint errors. Reuse them to trace FW-First Protocol errors. Since the CXL code is required to be called from process context and GHES is in interrupt context, use workqueues for processing. Similar to CXL CPER event handling, use kfifo to handle errors as it simplifies queue processing by providing lock free fifo operations. Add the ability for the CXL sub-system to register a workqueue to process CXL CPER protocol errors. [DJ: return cxl_cper_register_prot_err_work() directly in cxl_ras_init()] Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> Reviewed-by: Li Ming <ming.li@zohomail.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20250310223839.31342-2-Smita.KoralahalliChannabasappa@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
82 lines
2 KiB
C
82 lines
2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2025 AMD Corporation. All rights reserved. */
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#include <linux/pci.h>
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#include <linux/aer.h>
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#include <cxl/event.h>
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#include <cxlmem.h>
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#include "trace.h"
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static void cxl_cper_trace_corr_prot_err(struct pci_dev *pdev,
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struct cxl_ras_capability_regs ras_cap)
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{
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u32 status = ras_cap.cor_status & ~ras_cap.cor_mask;
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struct cxl_dev_state *cxlds;
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cxlds = pci_get_drvdata(pdev);
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if (!cxlds)
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return;
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trace_cxl_aer_correctable_error(cxlds->cxlmd, status);
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}
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static void cxl_cper_trace_uncorr_prot_err(struct pci_dev *pdev,
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struct cxl_ras_capability_regs ras_cap)
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{
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u32 status = ras_cap.uncor_status & ~ras_cap.uncor_mask;
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struct cxl_dev_state *cxlds;
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u32 fe;
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cxlds = pci_get_drvdata(pdev);
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if (!cxlds)
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return;
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if (hweight32(status) > 1)
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fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK,
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ras_cap.cap_control));
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else
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fe = status;
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trace_cxl_aer_uncorrectable_error(cxlds->cxlmd, status, fe,
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ras_cap.header_log);
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}
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static void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *data)
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{
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unsigned int devfn = PCI_DEVFN(data->prot_err.agent_addr.device,
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data->prot_err.agent_addr.function);
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struct pci_dev *pdev __free(pci_dev_put) =
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pci_get_domain_bus_and_slot(data->prot_err.agent_addr.segment,
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data->prot_err.agent_addr.bus,
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devfn);
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if (!pdev)
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return;
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guard(device)(&pdev->dev);
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if (data->severity == AER_CORRECTABLE)
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cxl_cper_trace_corr_prot_err(pdev, data->ras_cap);
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else
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cxl_cper_trace_uncorr_prot_err(pdev, data->ras_cap);
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}
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static void cxl_cper_prot_err_work_fn(struct work_struct *work)
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{
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struct cxl_cper_prot_err_work_data wd;
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while (cxl_cper_prot_err_kfifo_get(&wd))
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cxl_cper_handle_prot_err(&wd);
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}
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static DECLARE_WORK(cxl_cper_prot_err_work, cxl_cper_prot_err_work_fn);
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int cxl_ras_init(void)
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{
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return cxl_cper_register_prot_err_work(&cxl_cper_prot_err_work);
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}
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void cxl_ras_exit(void)
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{
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cxl_cper_unregister_prot_err_work(&cxl_cper_prot_err_work);
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cancel_work_sync(&cxl_cper_prot_err_work);
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}
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