mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-08-05 16:54:27 +00:00
317ab5b86c
This qdisc offload is the closest thing to what the SJA1105 supports in hardware for time-based egress shaping. The switch core really is built around SAE AS6802/TTEthernet (a TTTech standard) but can be made to operate similarly to IEEE 802.1Qbv with some constraints: - The gate control list is a global list for all ports. There are 8 execution threads that iterate through this global list in parallel. I don't know why 8, there are only 4 front-panel ports. - Care must be taken by the user to make sure that two execution threads never get to execute a GCL entry simultaneously. I created a O(n^4) checker for this hardware limitation, prior to accepting a taprio offload configuration as valid. - The spec says that if a GCL entry's interval is shorter than the frame length, you shouldn't send it (and end up in head-of-line blocking). Well, this switch does anyway. - The switch has no concept of ADMIN and OPER configurations. Because it's so simple, the TAS settings are loaded through the static config tables interface, so there isn't even place for any discussion about 'graceful switchover between ADMIN and OPER'. You just reset the switch and upload a new OPER config. - The switch accepts multiple time sources for the gate events. Right now I am using the standalone clock source as opposed to PTP. So the base time parameter doesn't really do much. Support for the PTP clock source will be added in a future series. Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
33 lines
1.2 KiB
Text
33 lines
1.2 KiB
Text
# SPDX-License-Identifier: GPL-2.0-only
|
|
config NET_DSA_SJA1105
|
|
tristate "NXP SJA1105 Ethernet switch family support"
|
|
depends on NET_DSA && SPI
|
|
select NET_DSA_TAG_SJA1105
|
|
select PACKING
|
|
select CRC32
|
|
help
|
|
This is the driver for the NXP SJA1105 automotive Ethernet switch
|
|
family. These are 5-port devices and are managed over an SPI
|
|
interface. Probing is handled based on OF bindings and so is the
|
|
linkage to PHYLINK. The driver supports the following revisions:
|
|
- SJA1105E (Gen. 1, No TT-Ethernet)
|
|
- SJA1105T (Gen. 1, TT-Ethernet)
|
|
- SJA1105P (Gen. 2, No SGMII, No TT-Ethernet)
|
|
- SJA1105Q (Gen. 2, No SGMII, TT-Ethernet)
|
|
- SJA1105R (Gen. 2, SGMII, No TT-Ethernet)
|
|
- SJA1105S (Gen. 2, SGMII, TT-Ethernet)
|
|
|
|
config NET_DSA_SJA1105_PTP
|
|
bool "Support for the PTP clock on the NXP SJA1105 Ethernet switch"
|
|
depends on NET_DSA_SJA1105
|
|
help
|
|
This enables support for timestamping and PTP clock manipulations in
|
|
the SJA1105 DSA driver.
|
|
|
|
config NET_DSA_SJA1105_TAS
|
|
bool "Support for the Time-Aware Scheduler on NXP SJA1105"
|
|
depends on NET_DSA_SJA1105
|
|
help
|
|
This enables support for the TTEthernet-based egress scheduling
|
|
engine in the SJA1105 DSA driver, which is controlled using a
|
|
hardware offload of the tc-tqprio qdisc.
|