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bab2d8c602
This series for the OpenRISC architecture consists of mostly trivial fixups.
The most interesting bits of the series are:
* A fix to the timer code whereby the shortest trigger period is set to
100 cycles; previously, it was possible to set this to 1 cycle, but by
the time the register was written, that time had already passed and the
timer interrupt would not go off until the cycle counter had gone a full
cycle.
* Allowing a device tree binary to be passed in to the kernel from u-boot.
The OpenRISC architecture has been recently merged into upstream u-boot,
so this change gets OpenRISC Linux into sync with that project.
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Merge tag 'for-3.4' of git://openrisc.net/jonas/linux
Pull OpenRISC changes for 3.4 from Jonas Bonn:
"This series for the OpenRISC architecture consists of mostly trivial
fixups. The most interesting bits of the series are:
* A fix to the timer code whereby the shortest trigger period is set
to 100 cycles; previously, it was possible to set this to 1 cycle,
but by the time the register was written, that time had already
passed and the timer interrupt would not go off until the cycle
counter had gone a full cycle.
* Allowing a device tree binary to be passed in to the kernel from
u-boot. The OpenRISC architecture has been recently merged into
upstream u-boot, so this change gets OpenRISC Linux into sync with
that project."
* tag 'for-3.4' of git://openrisc.net/jonas/linux:
OpenRISC: Remove memory_start/end prototypes
openrisc: remove semicolon from KSTK_ defs
openrisc: sanitize use of orig_gpr11
openrisc: fix virt_addr_valid
OpenRISC: Export dump_stack()
OpenRISC: Select GENERIC_ATOMIC64
openrisc: Set shortest clock event to 100 ticks
openrisc: included linux/thread_info.h twice
OpenRISC: Use set_current_blocked() and block_sigmask()
OpenRISC: Don't mask signals if we fail to setup signal stack
OpenRISC: No need to reset handler if SA_ONESHOT
OpenRISC: Don't reimplement force_sigsegv()
openrisc: enable passing of flattened device tree pointer
arch/openrisc/mm/init.c: trivial: use BUG_ON
|
||
|---|---|---|
| .. | ||
| boot | ||
| configs | ||
| include/asm | ||
| kernel | ||
| lib | ||
| mm | ||
| Kconfig | ||
| Makefile | ||
| README.openrisc | ||
| TODO.openrisc | ||
OpenRISC Linux
==============
This is a port of Linux to the OpenRISC class of microprocessors; the initial
target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k).
For information about OpenRISC processors and ongoing development:
website http://openrisc.net
For more information about Linux on OpenRISC, please contact South Pole AB.
email: info@southpole.se
website: http://southpole.se
http://southpoleconsulting.com
---------------------------------------------------------------------
Build instructions for OpenRISC toolchain and Linux
===================================================
In order to build and run Linux for OpenRISC, you'll need at least a basic
toolchain and, perhaps, the architectural simulator. Steps to get these bits
in place are outlined here.
1) The toolchain can be obtained from openrisc.net. Instructions for building
a toolchain can be found at:
http://openrisc.net/toolchain-build.html
2) or1ksim (optional)
or1ksim is the architectural simulator which will allow you to actually run
your OpenRISC Linux kernel if you don't have an OpenRISC processor at hand.
git clone git://openrisc.net/jonas/or1ksim-svn
cd or1ksim
./configure --prefix=$OPENRISC_PREFIX
make
make install
3) Linux kernel
Build the kernel as usual
make ARCH=openrisc defconfig
make ARCH=openrisc
4) Run in architectural simulator
Grab the or1ksim platform configuration file (from the or1ksim source) and
together with your freshly built vmlinux, run your kernel with the following
incantation:
sim -f arch/openrisc/or1ksim.cfg vmlinux
---------------------------------------------------------------------
Terminology
===========
In the code, the following particles are used on symbols to limit the scope
to more or less specific processor implementations:
openrisc: the OpenRISC class of processors
or1k: the OpenRISC 1000 family of processors
or1200: the OpenRISC 1200 processor
---------------------------------------------------------------------
History
========
18. 11. 2003 Matjaz Breskvar (phoenix@bsemi.com)
initial port of linux to OpenRISC/or32 architecture.
all the core stuff is implemented and seams usable.
08. 12. 2003 Matjaz Breskvar (phoenix@bsemi.com)
complete change of TLB miss handling.
rewrite of exceptions handling.
fully functional sash-3.6 in default initrd.
a much improved version with changes all around.
10. 04. 2004 Matjaz Breskvar (phoenix@bsemi.com)
alot of bugfixes all over.
ethernet support, functional http and telnet servers.
running many standard linux apps.
26. 06. 2004 Matjaz Breskvar (phoenix@bsemi.com)
port to 2.6.x
30. 11. 2004 Matjaz Breskvar (phoenix@bsemi.com)
lots of bugfixes and enhancments.
added opencores framebuffer driver.
09. 10. 2010 Jonas Bonn (jonas@southpole.se)
major rewrite to bring up to par with upstream Linux 2.6.36